AXIOMTEK IMB530 User Manual page 80

Register 1: Output port register.
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit
values in this register have no effect on pins defined as inputs. Reads from this register return
the value that is in the flip-flop controlling the output selection, not the actual pin value.
Bit Symbol
7 O7
6 O6
5 O5
4 O4
3 O3
2 O2
1 O1
0 O0
* : Default value
Register 2: Configuration register.
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this
register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are
configured as inputs with a weak pull-up to VDD.
Bit Symbol
7 C7
6 C6
5 C5
4 C4
3 C3
2 C2
1 C1
0 C0
* : Default value
80
Access Value
R 1*
R 1*
R 1*
R 1*
R 1*
R 1*
R 1*
R 1*
Access Value
R/W 1*
R/W 1*
R/W 1*
R/W 1*
R/W 1*
R/W 1*
R/W 1*
R/W 1*
Description
Reflects outgoing logic levels of pins defined as
outputs by Register 3.
Description
Configure the directions of the I/O pins.
0 = Corresponding port pin enabled as an output.
1 = Corresponding port pin configured as input
(default value).
Digital I/O