Pioneer VSX-AX5Ai-S Service Manual page 170

1
Pin Function
No. Pin Name I/O
1 V
DD2
A
2 BIAS
3 VRT
4 NC
5 AIN
6 VRB
7 V
DD3
B
8 V
SS2
9 NC
10 V
DD4
11 SDA
12 SCL
13 TEST
14 KILLER
C
15 CKIN
16 NC
17 FIL
18 V
DD1
19 V
SS1
20 C
OUT
D
21 NC
22 DAVRB
23 DAVRT
24 Y
OUT
E
F
170
1
2
−
ADC and DAC analog power supply
ADC bias voltage.
−
Stabilize by attaching a 0.01µF capacitor.
ADC input range D upper limit voltage.
−
Stabilize by attaching a 0.01µF capacitor.
−
Non connection
ADC input. Inputs 1.0 Vp-p video signal.
I
Sync tip clamp is performed.
ADC input range D lower limit voltage.
−
Stabilize by attaching a 0.01µF capacitor.
−
ADC and DAC logic power supply
−
Logic and internal DRAM GND (digital)
−
Non connection
−
Internal DRAM power supply
−
2
I C BUS SDA
−
2
I C BUS SCL
Shipment test mode switch or I
I When High, test mode, setting all I
Hold High for at least 100µs. Send I
Y signal comb function ON / OFF switch.
I When High, comb OFF. When Low, comb ON.
When [data 3 : bit 0] is 1, used as vertical edge enhancement circuit ON / OFF switch.
Clock input pin. This pin put a sine wave which is locked to the frequency of the burst signal in the input
video signal.
I
Amplitude is 300 mV p-p to 2 Vp-p.
Input as high an amplitude as possible without affecting peripheral circuits.
−
Non connection
O Connect the APC filter in the 8 fsc PLL circuit
−
PLL power supply
−
ADC, DAC, and PLL GND (analog)
O Outputs chrominance signal. External simple LPF for clock elimination recommended.
−
Non connection
DAC output range D lower limit voltage.
−
Stabilize by attaching a 0.01µF capacitor.
DAC output range D upper limit voltage.
−
Stabilize by attaching a 0.01µF capacitor.
O Outputs luminance signal. External simple LPF for clock elimination recommended.
2
3
Function
2
C bus setting reset pin.
2
C bus settings to 0.
2
C bus settings when this pin is Low.
VSX-AX5Ai-S
3
4
4