Parts - Pioneer VSX-AX5Ai-S Service Manual

5

7.2 PARTS

7.2.1 IC
• The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.
List of IC
PD8112A, PEG040B8, PEG041B, BU4094BCF, PCM2902EG, TSB43CA42, SM5819AF, TA1270BF, TC90A49F
PD8112A (1394 ASSY: IC301)
• Flow Control IC
Pin Function
No. Pin Name I/O
−
1 VDDOUT
2 SPDIFOUT O
3 SDATA3O O
4 SDATA2O O
5 SDATA1O O
6 SDATA0O O
7 LRCKOUT O
8 BCKOUT O
9 AMCLKOUT O
10 AMCLKEN O
11 SDERRO O
−
12 VSSOUT
−
13 VDDOUT
14 SDMUTEO O
15 SAPCMBCKIN I
16 SAPCMLRCKIN I
17 SAPCMD3IN I
18 SAPCMD2IN I
19 SAPCMD1IN I
20 SACDMKO O
21 SACDDAO O
22 SACDD0O O
23 SACDD1O O
24 SACDD2O O
25 SACDD3O O
−
26 VSSCORE
−
27 VDDCORE
28 SACDD4O O
29 SACDD5O O
30 SACDFRO O
31 TESTMODE0 I
32 TESTMODE1 I
33 PLLMODE I
34 SAPCMMODE I
35 XVALMODE I
36 RJMSBF I
37 SEL512 I
38 CONT48 O
39 CLK48K I
40 CLK48KI I
41 CLK48KO O
−
42 VSSOUT
−
43 VDDOUT
44 CONT44 O
45 CLK44K I
46 CLK44KI I
47 CLK44KO O
48 SELOSC I
5
6
Digital VDD (3.3V)
IEC60958 output
MBLA data output (5 ch, 6 ch) (at flow: I2S)
MBLA data output (3 ch, 4 ch) (at flow: I2S)
MBLA data output (1 ch, 2 ch) (at flow: I2S)
MBLA ancillary data output (at flow: I2S)
MBLA LRCK output
MBLA BCK output (64fs)
Master clock output (When AMCLKEN output is LOW, active Hi-Z.)
When 60958 is selected or OUTPUTEN=L output, active LOW. For external clock control
Data error flag output
Digital GND
Digital VDD (3.3V)
Data mute flag output MUTE: H
BCK input when converting SACD to MLPCM
LRCK input when converting SACD to MLPCM
DATA3 input when converting SACD to MLPCM
DATA2 input when converting SACD to MLPCM
DATA1 input when converting SACD to MLPCM
SACD master clock output (2.8224MHz)
SACD ancillary data output
SACD data output (L)
SACD data output (R)
SACD data output (C)
SACD data output (Lfe)
Digital GND (for inside)
Digital VDD (3.3V, for inside)
SACD data output (Ls)
SACD data output (Rs)
SACD frame data output (75Hz)
LSI test mode input Normally, "L" fixed
LSI test mode input Normally, "L" fixed
VCOCLK division ratio selection
0: normal, 1: When the data type is SACD, output SAPCM*** input to MLPCM.
0: 64M•128M bit SDRAM, 1: 256M bit SDRAM
MLPCM output format setting at flow
Master clock selection at flow 0: 768fs, 1: 512fs
Output for controlling the oscillator (When FMODE="1" and SEL44K="1", active High)
Master clock input of fs48kHz (36.864MHz or 24.576MHz)
Crystal resonator input of fs48kHz (24.576MHz)
Crystal resonator output of fs48kHz (24.576MHz)
Digital GND
Digital VDD (3.3V)
Output for controlling the oscillator (When FMODE="1" and SEL44K="0", active High)
Master clock input of fs44.1kHz (33.8688MHz or 22.5792MHz)
Crystal resonator input of fs44.1kHz (22.5792MHz)
Crystal resonator output of fs44.1kHz (22.5792MHz)
L: CLK4XK input selection, H: crystal resonator I/O selection As for the crystal resonator, less than
30MHz are insured.
VSX-AX5Ai-S
6
7
Pin Function
Normally, "L"
0: I2S, 1: Right aligned MSB first
7
8
A
B
C
D
E
F
145
8