Pioneer VSX-AX5Ai-S Service Manual page 162

1
No. Pin Name
A
142 HSDI0_DVALIDz
139 HSDI0_ENz
B
141 HSDI0_SYNCz
High Speed Data Interface (HSDI) Port 1 Pins
No. Pin Name
HSDI1_AMCLK_
169
IN
HSDI1_AMCLK_
C
170
OUT
HSDI1_AUDIO_
171
ERR
HSDI1_AUDIO_
172
MUTE
173 HSDI1_60958_IN
HSDI1_60958_
174
OUT
D
155 HSDI1_AVz
153 HSDI1_CLKz
E
158 HSDI1_D0
159 HSDI1_D1
163 HSDI1_D2
F
162
1
2
I/O
HSDI port 0 data valid pin. Programmable. Default active high. This pin indicates if data on the HSDI data
bus valid for reading or writing.
For transmit to 1394, this signal is provided by the system with the data.
I/O For receive from 1394, iceLynx-Micro provides this signal with the data.
For HSDI DV modes, this signal is used as HSDI0_FrameSync indicating DV frame boundary.
This signal is output to HSDI1_DVALIDz in pass-through mode.
If not used in transmit mode, this signal is pulled low.
HSDI port 0 enable. Programmable. Default active low. Input by the system to enable the HSDI for both
transmit to and receive from 1394.
I If not used, this signal is pulled enabled (low or high depending on the polarity set). The application can
use HSDI_DVALID or HSDI_SYNC to validate the HSDI data.
This signal is used as HSDI0_MLPCM_LRCLK for DVD-audio transmit.
HSDI port 0 sync signal. Programmable. Default active high. This signal indicates the start of packet.
For transmit to 1394, this signal is provided by the system with the data.
I/O For receive from 1394, iceLynx-Micro provides this signal with the data.
This signal is output to HSDI1_SYNCz in pass-through mode. If not used in transmit mode, this signal is
pulled low or high depending on the polarity.
I/O
Audio master clock input. This clock is used to decode the biphase encoding of 60958 data.
I This pin also inputs the 1.5*BCK for flow control mode. MLPCM interface, HSDI1 audio port, and HSDI1
video port share IsoPathBuffer 1. Only one interface can access the buffer at a time.
Audio master clock output. This clock is derived from the VCO_CLK input. 60958 data output from
O
iceLynx-Micro is biphase encoded using this clock.
Audio error signal. iceLynx-Micro asserts this signal whenever an audio error condition occurs. (Receive
O
from 1394 only.)
Audio mute status. iceLynx-Micro asserts this signal whenever an audio mute condition has occurred, and
O
hardware has muted the HSDI1 audio interface. (Receive from 1394 only.)
I 60958 data input
60958 data output
O
This signal is also used as FLWCTRL_DVALID in flow control data valid mode.
HSDI port 1 available. Programmable. Default active low.
For receive from 1394, this signal indicates if a 1394 packet is available in the receive buffer for reading.
The HSDI_AV signal for MPEG2 data also depends on time stamp based release.
O
For transmit to 1394, this signal indicates the buffer level in HSDI TX modes 8 and 9 by programming a
CFR. This pin indicates buffer level in transmit mode by programming a CFR. If the buffer level is above a
programmed level, HSDI_AV is asserted.
HSDI port 1 clock. Programmable. Default rising edge sample.
This clock is used to operate the HSDI port 1 logic. In parallel mode, the maximum clock is 27 MHz.
In serial mode, the maximum clock is 70 MHz.
I/O
This signal is used as HSDI1_SACD_BCLK for SACD transmit and receive.
MLPCM interface, HSDI1 audio port, and HSDI1 video port share IsoPathBuffer 1. Only one interface can
access the buffer at a time.
HSDI port 1 data 0 pin. Data 0 is the least significant bit on the HSDI data bus. In serial mode, only
I/O HSDI0_D0 is used.
This signal is used as HSDI1_SACD_D0 for SACD transmit and receive.
I/O HSDI port 1 data 1 pin. This signal is used as HSDI1_SACD_D1 for SACD transmit and receive.
I/O HSDI port 1 data 2 pin. This signal is used as HSDI1_SACD_D2 for SACD transmit and receive.
VSX-AX5Ai-S
2
3
Pin Function
Pin Function
3
4
4