Pioneer VSX-AX5Ai-S Service Manual page 146

1
No. Pin Name
49 XRESET
A
50 OUTPUTEN
51 FMODE
52 SELDTYPE0
53 SELDTYPE1
54 SEL44K
55 FSSEL0
56 FSSEL1
57 VSSOUT
58 VDDOUT
59 RXSTART
60 SACDCHSEL
B
61 FMUTE
62 FSTATE0
63 FSTATE1
64 FSTATE2
65 TDI
66 TDO
67 TMS
68 TCK
69 TRST
C
70 SACDMKIN
71 SACDFRIN
72 SACDD0IN
73 VSSCORE
74 VDDCORE
75 SACDD1IN
76 SACDD2IN
77 SACDD3IN
78 SACDD4IN
79 SACDD5IN
D
80 SACDDAIN
81 AMCLKIN
82 SPDIFIN
83 SDMUTEIN
84 SDERRIN
85 VCOCLK2O
86 VCOCLK1O
87 REFSYT
88 DIVVCO
89 VCOEN
90 VSSCORE
E
91 VDDCORE
92 VSSOUT
93 VSSPASS
94 VDDPASS
95 LPOUT
96 LPIN
F
146
1
2
I/O
I Logic reset input Reset for L
I Pin for controlling the audio system output H: output, L: Hi-Z
I Flow mode control input at flow: H, at through: L
I Data type input 0 00: IEC60958, 01: MBLA
I Data type input 1 1X: SACD
I Selecting signal of master clock input at flow
I fs setting input 0 00: 44.1/48kHz, 01: 88.2/96kHz
I fs setting input 1 10: 176.4/192kHz, 11: 29.4/32kHz
−
Digital GND
−
Digital VDD (3.3V)
I Trigger signal input of flow receiving start
I In a through mode, set to 1 in SACD 5 channel receiving. 0: 2ch•6 ch, 1: In 5ch flow receiving, a channel
is distinguished automatically by ansillary data.
I Forced mute control signal input
O Status output 0 of memory in the flow
O Status output 1 of memory in the flow 00: Empty < 01: fast < 11: standard < 10: slow • full
Status output 2 of flow receive data When received data type to be different from the set data type,active
O
High.
I Boundary Scan TAP pin
O Boundary Scan TAP pin
I Boundary Scan TAP pin
I Boundary Scan TAP pin
I Boundary Scan TAP pin
I SACD bit clock input
I SACD frame signal input
I SACD data input 0 (ch1)
−
Digital GND (for inside)
−
Digital VDD (3.3V, for inside)
I SACD data input 1 (ch2)
I SACD data input 2 (ch3)
I SACD data input 3 (ch4)
I SACD data input 4 (ch5)
I SACD data input 5 (ch6)
I SACD ansillary data input
I Master clock input (VCO) at through mode
I IEC60958 input Data valid input at flow
I Mute flag input at through mode
I Data error flag input
O VCO clock output 2 (for 512fs)
O VCO clock output 1 (for 768fs)
I PLL reference input (at passive filter)
I PLL VCO dividing input (at passive filter)
I Built-in VCO control input
−
Digital GND (for inside)
−
Digital VDD (3.3V, for inside)
−
Connect to analog GND
−
Analog GND
−
Analog VDD (3.3V)
O Phase comparator output (analog)
I VCO control voltage input (analog)
VSX-AX5Ai-S
2
3
Function
L: CLK48K, H: CLK44K
Reflect to SDMUTEO.
Low: stop, High: oscillation
3
4
4