Sony HBD-E385 Service Manual page 76

HBD-E385/E390/T39
Pin No. Pin Name
P4 NO_USE
P5 NO_USE
P6 NO_USE
P7 A1
P8 A4
P9 VSS
R1 VDD
R2 A7
R3 A9
R4 NO_USE
R5 NO_USE
R6 NO_USE
R7 A11
R8 A6
R9 VDD
T1 VSS
T2 RESET
T3 A13
T4 NO_USE
T5 NO_USE
T6 NO_USE
T7 NC
T8 A8
T9 VSS
76
I/O
- Not used
- Not used
- Not used
Address inputs: Provided the row address for active commands and the column address for
I Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Address inputs: Provided the row address for active commands and the column address for
I Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
- Ground
- Power Supply: 1.5V +/-0.075
Address inputs: Provided the row address for active commands and the column address for
I Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Address inputs: Provided the row address for active commands and the column address for
I Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
- Not used
- Not used
- Not used
Address inputs: Provided the row address for active commands and the column address for
I Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Address inputs: Provided the row address for active commands and the column address for
I Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
- Power Supply: 1.5V +/-0.075
- Ground
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when
RESET is HIGH. RESET must be HIGH during normal operation. RESET is CMOS rail to rail
I
signal with DC high and low at 80% and 20% of V
for DC low.
Address inputs: Provided the row address for active commands and the column address for
I Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
- Not used
- Not used
- Not used
- No Connect: No internal electrical connection is present.
Address inputs: Provided the row address for active commands and the column address for
I Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
- Ground
Description
, example, 1.20V for DC high and 0.30V
DD