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LG 42PQ20 Training Manual
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LG 42PQ20 Training Manual

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Training Manual
42PQ20 Plasma Display
42PQ20 Plasma Display
Advanced Single Scan Troubleshooting
720p
720p
NOTICE:
ALL INFORMATION CONTAINED WITHIN THIS PACKAGE IS BASED ON PRE-
SALES MODEL. INFORMATION SUBJECT TO CHANGE AT FINAL PRODUCTION
Updated: September 23
, 2009
rd

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Summary of Contents for LG 42PQ20

  • Page 1 Training Manual 42PQ20 Plasma Display 42PQ20 Plasma Display Advanced Single Scan Troubleshooting 720p 720p NOTICE: ALL INFORMATION CONTAINED WITHIN THIS PACKAGE IS BASED ON PRE- SALES MODEL. INFORMATION SUBJECT TO CHANGE AT FINAL PRODUCTION Updated: September 23 , 2009...
  • Page 2 • Y Drive Boards (Receives Y Drive signals from Y-SUS PWB) • Z SUS Output Board (Connects directly with FPC to Panel) • Control Board • X Drive Boards (2) • Main Board • Main Power Switch, deactivates all inputs from IR or Keys January 2009 Plasma 42PQ20...
  • Page 3 Overview of Topics to be Discussed Overview of Topics to be Discussed 42PQ20 Plasma Display Section 1 This Section will cover Contact Information and remind the Technician of Important Safety Precautions for the Customers Safety as well as the Technician and the Equipment.
  • Page 4 When servicing this product, under no circumstances should the original design be modified or altered without permission from LG Electronics. Unauthorized modifications will not only void the warranty, but may lead to property damage or user injury. If wires, screws, clips, straps, nuts, or washers used to complete a ground path are removed for service, they must be returned to their original positions and properly fastened.
  • Page 5 Increase the separation between the equipment and the receiver; Connect the equipment to an outlet on a different circuit than that to which the receiver is connected; or consult the dealer or an experienced radio/TV technician for help. January 2009 Plasma 42PQ20...
  • Page 6 New Training Materials on Alignment Handbook Plasma page Plasma page the Learning Academy site the Learning Academy site Published January 2009 by LG Technical Support and Training LG Electronics Alabama, Inc. 201 James Record Road, Huntsville, AL, 35813. January 2009 Plasma 42PQ20...
  • Page 7 1. Check the appearance of the Replacement Panel and Circuit Boards for both physical damage and part number accuracy. 2. Check the model label. Verify model names and board model matches. 3. Check details of defective condition and history. Example: Oscillator failure dead set, etc… January 2009 Plasma 42PQ20...
  • Page 8 The final step is to correct the problem. Be careful of ESD and make sure to check the DC Supplies for proper levels. Make all necessary adjustments and lastly always perform a Safety AC Leakage Test before returning the product back to the Customer. January 2009 Plasma 42PQ20...
  • Page 9 42PQ20 Product Information 42PQ20 Product Information This section of the manual will discuss the specifications of the 42PQ20 Advanced Single Scan Plasma Display Panel. January 2009 Plasma 42PQ20...
  • Page 10 • Fluid Motion • 3x HDMI™ V.1.3 with Deep Color • AV Mode (Cinema, Sports, Game) • Clear Voice • LG SimpLink™ Connectivity • Invisible Speaker System • 100,000 Hours to Half Brightness (Typical) • PC Input January 2009 Plasma...
  • Page 11 Vertical Grids a single Colored Cell Vertical Grids Determine Horizontal X-Boards X-Boards Resolution “TCPs” Same as (A-BUS) Initialize the Cell Deliver Color information Vertical Grids are in “Back” of the Cells as viewed from the front. January 2009 Plasma 42PQ20...
  • Page 12 1365 (H) × 768 (V) Interlaced Possible Frame 2 Fields to make a Frame Rates: 24FPS 1080P Panel Progressive 30FPS 1920 (H) x 1080 (V) Each Field is a Frame 60FPS Think of sync as the Panels “Refresh Rate” January 2009 Plasma 42PQ20...
  • Page 13 10.2Gbps) than that of HDMI 1.2, delivering a broader range of colors, and also drastically improves the data-transmission speed. Invisible Speaker Personally tuned by Mr. Mark Levinson for LG TAKE IT TO THE EDGE newly introduces ‘Invisible Speaker’ system, guaranteeing first class audio quality personally tuned by Mr. Mark Levinson, world renowned as an audio authority.
  • Page 14 42PQ20 Specifications Logo Familiarization 42PQ20 Specifications Logo Familiarization AV Mode "One click" - Cinema, Sports, Game mode. TAKE IT TO THE EDGE is a true multimedia TV with an AV Mode which allows you to choose from 3 different modes of Cinema, Sports and Game by a single click of a remote control.
  • Page 15 Digital is the reigning standard for surround sound technology in general and 5.1-channel surround sound in particular. LG SIMPLINK™ MULTI-DEVICE CONTROL Allows for convenient control of other LG SimpLink products using the existing HDMI connection. FluidMotion (180 Hz Effect) Enjoy smoother, clearer motion with all types of programming such as sports and action movies.
  • Page 16 42PQ20 Specifications FluidMotion Familiarization 42PQ20 Specifications FluidMotion Familiarization FluidMotion (180 Hz Effect) Enjoy smoother, clearer motion with all types of programming such as sports and action movies. The moving picture resolution give the impression of performance of up to 3x the panels actual refresh rate.
  • Page 17 42PQ20 Remote Control 42PQ20 Remote Control BOTTOM PORTION TOP PORTION January 2009 Plasma 42PQ20...
  • Page 18 Rear and Side Input Jacks Rear and Side Input Jacks Software Upgrades AC In January 2009 Plasma 42PQ20...
  • Page 19 42PQ20 Product Dimensions 42PQ20 Product Dimensions Wattage There must be at least 4 inches of Clearance on all sides 3.1/8" Average: 181W 78.7mm 40.5/8" Stby: 0.13W 1031mm 4.1/16" 104mm 15.3/4" 400mm 12.3/16" 310mm 15.3/4" 400mm 15.3/4" Center 400mm Model No.
  • Page 20 DISASSEMBLY SECTION This section of the manual will discuss Disassembly, Layout and Circuit Board Identification, of the 42PQ20 Advanced Single Scan Plasma Display Panel. Upon completion of this section the Technician will have a better understanding of the disassembly procedures, the layout of the printed circuit boards and be able to identify each board.
  • Page 21 42PQ20 Removing the Back Cover 42PQ20 Removing the Back Cover To remove the back cover, remove the 26 screws (The Stand does not need to be removed). Indicated by the arrows. PAY CLOSE ATTENTION TO THE TYPE, SIZE AND LENGTH Of the screws when replacing the back cover.
  • Page 22 42PQ20 Circuit Board Layout 42PQ20 Circuit Board Layout Panel Voltage Label Panel ID Label Y Drive Power Supply (SMPS) PWB Z-SUS PWB Y SUS PWB Side Input (part of main) Control PWB Heat Sink Main PWB AC In Right “X”...
  • Page 23 Signal and Voltage Distribution Signal and Voltage Distribution January 2009 Plasma 42PQ20...
  • Page 24 Remove the PWB by lifting slightly and sliding the PWB to the left unseating P204 and P200 from the Y-SUS PWB. Note: PWB stand-offs have a small collar. The board must be lifted slightly to clear these collars. January 2009 Plasma 42PQ20...
  • Page 25 Remove the 6 screws holding the Heat Sink in place. Rock back and slide down to remove. Disconnect the following connectors: P201 through P206 and P301 through P306 Remove the 3 screws holding each of the X Drive PWBs in place (8 total) Remove the PWBs. January 2009 Plasma 42PQ20...
  • Page 26 Disconnect all TCP ribbon cables from the defective X-Drive PWB. Remove the 4 screws holding the PWB in place. Remove the PWB. Reassemble in reverse order. Recheck Va / Vs / VScan / -VY / Z-Drive. January 2009 Plasma 42PQ20...
  • Page 27 (1) Pull Metal Frame back slightly (2) Pull Heat Sink back slightly and align stationary collar. Then pull up. Do the same for the other side. Right Left Heat Sink Notch Heat Sink Lower Metal Frame January 2009 Plasma 42PQ20...
  • Page 28 Gently pry the locking mechanism upward and remove the ribbon cable from the connector. Removing TCPs. Carefully lift the TCP ribbon up and off. Gently lift the locking mechanism upward on all TCP connectors P201~206 or P301~306 Cushion (Chocolate) Flexible ribbon cable January 2009 Plasma 42PQ20...
  • Page 29 Lift up the lock as shown by arrows. (The Lock can be easily broken. It needs to be handled carefully.) Pull TCP apart as shown by arrow. (TCP Film can be easily damaged. Handle with care.) January 2009 Plasma 42PQ20...
  • Page 30 Remove the 4 screws for either PWB or 7 total for both. (The Center screw secures both PWBs) Left X Board drives the right side of the screen Right X Board drive the left side of the screen January 2009 Plasma 42PQ20...
  • Page 31 CIRCUIT OPERATION, TROUBLESHOOTING AND ALIGNMENT SECTION CIRCUIT OPERATION, TROUBLESHOOTING AND ALIGNMENT SECTION 42PQ20 Plasma Display This Section will cover Circuit Operation, Troubleshooting and Alignment of the Power Supply, Y-SUS Board, Y Drive Boards, Z-SUS Board, Control Board, Main Board and the X Drive Boards.
  • Page 32 (4) Adjusting Voltage DC, Va, Vs (12) Model Name (5) Adjusting Voltage (Set Up / -Vy / Vsc / Ve / Vzb) (13) Max. Watt (Full White) (6) Trade name of LG Electronics (14) Max. Volts (7) Manufactured date (Year & Month) (15) Max. Amps...
  • Page 33 1) When the Y-SUS PWB is replaced 2) When a “Mal-Discharge” problem is encountered All label references are from a specific panel. 3) When an abnormal picture issues is encountered They are not the same for every panel encountered. January 2009 Plasma 42PQ20...
  • Page 34 Hand side for the correct voltage levels for the VA, VS, -VY, Vscan, and Z Bias as these voltages will vary from Panel to Panel even in the same size category. • Set-Up and Ve are just for Label location identification and are not adjusted in this panel. January 2009 Plasma 42PQ20...
  • Page 35 Power Supply PWB Layout Power Supply PWB Layout Hot Ground Symbol represents a SHOCK Hazard P811 P813 AC Det 5V Det RL ON VS ON M5 ON Auto Gnd Key On 23 Stby5V January 2009 Plasma 42PQ20...
  • Page 36 There are 2 adjustments located on the Power Supply Board VA and VS. The 5V VCC is pre-adjusted and fixed. All adjustments are made with relation to Chassis Ground. Use “Full White Raster” 100 IRE RV901 Adjustments RV951 January 2009 Plasma 42PQ20...
  • Page 37 VA Source VS Source 90V Stby 340V Run Fuse F801 VS VR901 4Amp/250V VA VR502 380V Source 17V, 12V Main Fuse Standby IC701 Source F101 Source Sub Micon 6.3Amp/250V P813 AC Input SC 101 To MAIN January 2009 Plasma 42PQ20...
  • Page 38 VS-ON line high at Pin 20 of P813 on the SMPS Board which when sensed by the Sub Micon IC (IC701) turns on the VA and VS Supplies (VA pins 6 and 7 is brought high before VS pins 1 and 2) and output from P811 to the Y-SUS board. January 2009 Plasma 42PQ20...
  • Page 39 42PQ20 POWER SUPPLY START UP SEQUENCE 42PQ20 POWER SUPPLY START UP SEQUENCE POWER SUPPLY Y-SUS PWB (SMPS) M5V (DC Voltage) Also develops 15V In Stand-By In Run (Relay On) Primary side is Primary side is AC In 370V Vs/Va (DC Voltage)
  • Page 40 Audio would be present. If VS-ON went high and VS and VA where missing the problem could be caused by a failure on the SMPS or a circuit using these voltages. A Resistance check should narrow the possible failures quickly. January 2009 Plasma 42PQ20...
  • Page 41 (Remember, Vs is routed to the Z-SUS PWB P3 from the Y-SUS P206 pins 1 & 2. This will allow the Y-SUS to function. Also, if you unplug the Y-SUS from the SMPS and jump the 5V VCC line to any 5V location on the Control Board the Control PWB will function. January 2009 Plasma 42PQ20...
  • Page 42 Static Test Under Load (Light Bulb Test) Static Test Under Load (Light Bulb Test) January 2009 Plasma 42PQ20...
  • Page 43 (D) 100Ω ¼ watt resistor added from 5V STB (Pins 9 ~ 12) to VS ON (Pin 20) brings the VA and VS (P811 pins 1 and 2 Vs and Pins 6 and 7 Va) Lines high January 2009 Plasma 42PQ20...
  • Page 44 But, check using 200W light bulb test. Va TP Panel Voltage Label P811 Pin 6 or 7 Vs TP P811 Pin 1 or 2 Important: Use the Panel Label Not this book for all voltage adjustments. January 2009 Plasma 42PQ20...
  • Page 45 Open 1 and 3 P811 CONNECTOR "Power Supply PWB“ to Y-SUS Label STBY Diode Mode *193V Open *193V Open *60V Open *60V Open 2.99V 2.99V * Note: This voltage will vary in accordance with Panel Label January 2009 Plasma 42PQ20...
  • Page 46 AC Det 1.0V 5V Det 3.1V Vs On 3.2V Open RL On 3.73V Open AUTO Open M5 ON 3.26V Open Key On Open Stby5V Open Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 47 Ramp UP sets amplitude of the Top Ramp of the Drive Waveform V SET DN VR602 V Set Down sets the Pitch of the Bottom Ramp of the Drive Waveform To the Control Board then routed to the Z-SUS board Floating Ground Used on the Y-Drive boards January 2009 Plasma 42PQ20...

  • Page 48: Table Of Contents

    Pins 4 and 5 P207 from the Control PWB Pins 7, 8, 9, 10 and 11 VSC ADJ Logic (Drive) Signals to -VY ADJ VR501 FS501 Va to Left X Board the Y Drive PWBs VR502 (15V) 4A P202 January 2009 Plasma 42PQ20...

  • Page 49: P207 Pins 1 And 2

    Pins 4 or 5 P207 7. CLK 8. STB 9. OC1 P104 P207 10. DATA 11. n/c P207 Pins 7, 8, 9, 10 and 11 Bottom Connector P207 12. SUS_Dn Logic (Drive) Signals to the Y Drive PWB January 2009 Plasma 42PQ20...

  • Page 50: Vsc Tp R520 / J263

    Set should run for 15 minutes, this is the “Heat Run” mode. Set screen to “White Wash” mode or 100 IRE White input. Adjust –Vy to Panel Label voltage (+/- 1V) Adjust VSC to Panel Label voltage (+/- 1V) Lower Left Side of PWB January 2009 Plasma 42PQ20...
  • Page 51 NOTE: The two test points just below and to the left will also work for the Y-Drive waveform Test Point. January 2009 Plasma 42PQ20...
  • Page 52 At 400us per/div. the signal for is now easier to SET-UP 400uS recognize. It is outlined within the Waveform Fig 4: At 40uSec per/division, the adjustment for FIG4 can be made. 40uS SET-UP Area to be adjusted January 2009 Plasma 42PQ20...

  • Page 53: Set Dn

    At 400us per/div. the signal for is now easier to SET-DN 400uS recognize. It is outlined within the Waveform Fig 4: At 40uSec per/division, the adjustment for SET-DN FIG4 can be made. 40uS Area to be adjusted January 2009 Plasma 42PQ20...
  • Page 54 Y SUSTAIN ADJUSTMENT DETAILS (Vs, Va, VSC and –VY must have already been completed). Set in White Wash. Observe the Picture while making these adjustments. Normally, they do not have to be done. Y-Drive PWB Test Point ADJUSTMENT LOCATION: Just to the bottom right of the right hand heat sink. January 2009 Plasma 42PQ20...
  • Page 55 Peeking too late and alters the start of the Vset DN phase. Very little alteration to the picture, the wave form indicates a Ramp (Vset UP) too low distorted Vset UP. The peek widens due to the Vset UP peeking too quickly. January 2009 Plasma 42PQ20...
  • Page 56 PWB and make necessary adjustments. All of the center washes out due to increased Vset_DN time. Vset DN too high The center begins to wash out and arc due to decreased Vset DN too low Vset DN time. January 2009 Plasma 42PQ20...
  • Page 57 Circuits generate from Vs by DC/DC Converters Y Sustain Waveform Also controls Ramp Up/Down Generates Floating Ground Left X Board 5V by DC/DC Converters FETs amplify Sustain Waveform Y Drive Board Display Panel Receives Scan Waveform January 2009 Plasma 42PQ20...
  • Page 58 Reverse: Open 30N45T 30N45T IRGP4086 Forward: 0.6V Forward: 0.6V Forward: 0.39V ~ 0.5V Reverse: Shorted Reverse: Shorted Reverse: Open K3667 K3667 K3667 Forward: 0.4V ~ 0.5V Forward: 0.22V Forward: 0.5V Reverse: Open Reverse: Open Reverse: Open January 2009 Plasma 42PQ20...
  • Page 59 STBY Diode Mode *193V Open *193V Open *60V Open *60V Open 1.1V 1.1V * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 60 P202 CONNECTOR "Y-SUS PWB" to "X-Drive” Left P233 Label STBY Diode Mode *60V Open *60V Open *60V Open * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 61 Diode Mode Er Com * 94.9V Open Er Com *94.9V Open *193V Open *193V * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 62 Standby: 0V Run: 5V Diode Check: 1.1V FS501 15V to run the Z-SUS Board. Routed through the Control Board. Leaves the Control Board on P101 pins 11 and 12. Standby: 0V Run: 15V Diode Check: 0.78V January 2009 Plasma 42PQ20...
  • Page 63 Dummy 3 Dummy 1 0.6V 0.65V 0.17V 0.65V Dummy 5 2.96V 0.65V 2.5V 0.65V Set_Up 1.4V 0.65V 0.65V ER_DN 0.65V 0.65V Data SUS-DN 1.89V 0.65V Open 2.16V 0.65V Dummy 2 0.44V 0.44V 0.44V 0.44V 0.44V Open Open January 2009 Plasma 42PQ20...
  • Page 64 Pin Label Voltage 1) VSC 140V 2) VSC 140V 3) Nc 4) 5V VF 5) 5V VF 6) SUS_DN FGnd 7) CLK 0.96V 8) STB 2.3V 9) OC1 2.3V 10) DATA 11) Nc 12) SUS_DN FGnd January 2009 Plasma 42PQ20...
  • Page 65 0.59V 9.) OC1 1.67V 0.63V 10.) Data 1.57V 0.59V 11.) nc 1.67V 0.65V Floating Gnd 12.) SUS Dn Pin 1 Pin 1 on Y-SUS is backwards Floating compared to Ground Meter in the Diode Mode Y-Drive January 2009 Plasma 42PQ20...
  • Page 66 Y SUSTAIN PWB and sent to the Panel through SCAN DRIVER IC’s. The Y Drive Boards supply a waveform which selects the horizontal electrodes sequentially. * 42PQ20 uses 8 DRIVER ICs on 1 Y Drive Board Y DRIVE WAVEFORM Y DRIVE WAVEFORM TEST POINT To facilitate scope attachment, solder a small wire (Stand Off) at this point.
  • Page 67 P101 P103 P102 P104 BOTTOM Y Drive Scan (VSC) Signal Input TP PANEL Pins 11 and 12 of P104 SIDE Check 5V supply using FL1 or across C18. Measured from Floating Ground Floating Gnd 5V Protect January 2009 Plasma 42PQ20...
  • Page 68 7) SUS_DN FGnd 6) SUS_DN FGnd 6) CLK 0.96V 7) CLK 0.96V 5) LE 2.3V 8) STB 2.3V 4) OC1 2.3V 9) OC1 2.3V 3) DATA 10) DATA 2) Nc 11) Nc 1) SUS_DN FGnd 12) SUS_DN FGnd January 2009 Plasma 42PQ20...
  • Page 69 2.9V 4.) OC1 0.5V Open 3.) Data 0.62V Open 2.) nc 0.48V Open Floating Gnd 1.) SUS Dn Pin 1 Pin 1 on Y-SUS is backwards Floating compared to Meter in the Diode Mode Ground Y-Drive January 2009 Plasma 42PQ20...
  • Page 70 To reinstall the Ribbon Cable, carefully slide it back into the slot see ( Fig 3 ), be sure the Tab is seated securely and press the Locking Tab back to the locked position see ( Fig 2 then Fig 1). January 2009 Plasma 42PQ20...
  • Page 71 Note the cable is crooked. In this case the Tab on the Ribbon cable was improperly seated at the top. This can cause bars, lines, intermittent lines abnormalities in the picture. Remove the ribbon cable and re-seat it correctly. January 2009 Plasma 42PQ20...
  • Page 72 43 42 128 Output Pins per/buffer • Any of these output lugs can be tested. 6 Ribbon cables (Horizontal Grids) • Look for shorts indicating a defective Buffer IC 768 Total Horizontal Grids controlling Vertical resolution January 2009 Plasma 42PQ20...
  • Page 73 Locations Locations • DC Voltage and Waveform Test Points • Z BIAS Alignment • Resistance Test Points Operating Voltages Operating Voltages Y SUS Supplied 5V Vcc Developed on Y SUS Z Bias January 2009 Plasma 42PQ20...
  • Page 74 Z SUS Waveform Waveform Test Point Development Z SUS Output VS Input from the Y-SUS Z-Bias ADJ VR8 VZ (Z-Bias) TP Right side R49 or R50 Logic Signals from the Control PWB Also +15V and +5V January 2009 Plasma 42PQ20...
  • Page 75 J27 to check Z Output waveform. Right Hand side Center. Vzb voltage + - 1V 80 V 50V/div 400uS/div Note: The Vzb Adjustment is a DC level adjustment This Waveform is just for reference to observe the effects of Zbz adjustment January 2009 Plasma 42PQ20...
  • Page 76 Side R49 or R50 Set should run for 15 minutes, this is the “Heat Run” mode. Set screen to “White Wash” mode or 100 IRE White input. Measured from Chassis Ground Adjust VZ (Z-Bias) to Panel Label (± 1V) January 2009 Plasma 42PQ20...
  • Page 77 5V, 15V Z-SUS PWB Receives VS from 5V, 15V Y-SUS and 15V, 5V from Control PWB Circuits generate erase, Generates Z Bias 100V sustain waveforms Display Panel FET Makes Drive waveform Via FPC (flexible printed circuit ) January 2009 Plasma 42PQ20...
  • Page 78 ER COM *94.9V Open ER COM *94.9V Open Open Open *193V Open *193V Open * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 79 Z ER DN 0.4V 1.9V Z BIAS 1.9V 1.9V Z ENABLE 0.8V Open Z RAMP DN 1.9V Open 4.9V Open +15V 16.9V Open +15V 16.9V Open Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 80 Resistance Test Points Signals Signals Main Board Supplied LVDS Signal Operating Voltages Operating Voltages Y SUS Supplied +5V (Also Routed to the Z-SUS) +15V (Routed to the Z-SUS) Developed on the +1.8V Control board (2) +3.3V January 2009 Plasma 42PQ20...
  • Page 81 Download Connection P121 P131 1.8V 3.3V IC221 To P101 IC121 IC231 Y-SUS 3.3V Part Number Label P111 IC201 P101 To P2 Z-SUS D201 AUTO GEN TEST Data Vs DA PATTERN 3.2V P161 P162 To X Drive Left January 2009 Plasma 42PQ20...
  • Page 82 5V which under normal operation supplies the Control Board with 5V via the Y SUS Board. By using 5V STB, the following test will confirm Normal operation of the Control Board if that supply is missing. January 2009 Plasma 42PQ20...
  • Page 83 If there is a picture of cycling colors, the Y-SUS, Y-Drive, Z-SUS, Power Supply, Control PWBs and Panel are all OK. Same test for (2) to tell if the No Video is caused by the Main PWB. January 2009 Plasma 42PQ20...
  • Page 84 1.5V ~ 1.8V Osc. Check: 25Mhz Check the output of the Oscillator package. The frequency of the sine wave is 25.25 MHZ. Missing this clock signal can halt operation of the unit CONTROL PWB CRYSTAL LOCATION January 2009 Plasma 42PQ20...
  • Page 85 Menu Button “on” and “off” with the Remote Control or Keypad. Loss of these Signals would confirm the failure is on the Main Board! Menu ON Menu Off Example of Normal Signals measured at 200mv/cm at 5µs/cm. P1002 on Main Board January 2009 Plasma 42PQ20...
  • Page 86 CONTROL PWB X-DRIVE PWB Resistor Array EEPROM DRAM 16 line IC201 2 Buffer PANEL Outputs per TCP 128 Lines per Buffer 256 Lines output Total To X-Drive Boards January 2009 Plasma 42PQ20...
  • Page 87 Removing the LVDS Cable from the Control PWB The LVDS Cable has two “Interlocks” that must be disengaged to remove the LVDS Cable. To Disengage, press the two Locking Tabs Inward and pull the plug out. Press Press Inward Inward January 2009 Plasma 42PQ20...
  • Page 88 Pins 3, 4, 5, 6, and 7 and 12. Receive +5V from the Y-SUS. Pins 9, 10, 11 and 30 Are Ground All the rest are delivering Y-Drive logic signals to the Y-SUS Board Even Pins Pins January 2009 Plasma 42PQ20...
  • Page 89 0.65V Dummy 1 1.05V 0.65V Dummy 3 0.65V ER_UP 0.2V 0.65V Dummy 4 1.28V 0.65V SUS_UP 0.13V 0.65V CTRL_OE 0.1V 0.65V SET_DN 0.12V 0.65V Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 90 Z Bias 0.19V 0.65V Z Enable 0.08V 0.65V Z Ramp Dn 0.19V 0.65V 4.9V 0.43V Open Pin 1 at the bottom of the connector Open Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 91 These pins are covered with tape for transportation issues. (Tape can be removed). P162 P161 Tape removed 3.3V 3.3V The rest of the pins are much too 3.3V created close together for a safe test. 3.3V by IC221 January 2009 Plasma 42PQ20...
  • Page 92 BUS) The X Drive PWBs deliver the Color drive signals to the Vertical Grids. The 42PQ20 has a Left and a Right X-Drive board. Each with 6 connectors to a TCP. And each TCP with 2 buffers. Each buffer controls 128 vertical grids lines.
  • Page 93 After a very short time, these ICs will begin to self destruct due to overheating. LEFT X BOARD P233 P211 P232 TCP IC RIGHT X BOARD P331 P311 TCP IC TCP IC’s shown are part of the Ribbon Cable January 2009 Plasma 42PQ20...
  • Page 94 TCP ICs supply RGB 16 bit signal to the PDP by connecting the PAD Electrode of the PANEL with the X Board. X Drive Board Y-SUS Board Logic Control Board Taped Carrier Package Heat Sink Back side of TCP Ribbon January 2009 Plasma 42PQ20...
  • Page 95 TCP Testing TCP Testing On any Gnd 10,11,12,13,14,27,28,2 Typical Reverse leads 9,30,37,38,39,40,41 Reading 0.65V Reading Open On any Va 4,5,6,7,44,45,46,47 Look for any TCPs being discolored. Ribbon Damage. Cracks, folds Pinches, scratches, etc… January 2009 Plasma 42PQ20...
  • Page 96 Generate abnormal vertical bars c) Cause the entire area driven by the TCP to be “All White” d) Cause the entire area driven by the TCP to be “All Black” e) Cause a “Single Line” defect January 2009 Plasma 42PQ20...
  • Page 97 5V 3.3V 0V 3.3V Check for 3.3V Check for 3.3V P232 P331 Top C231 Top C363 Left Left C307 C206 Left X PWB Right X PWB 3.3V in on Pins 49-50-51 3.3V in on Pins 49-50-51 January 2009 Plasma 42PQ20...
  • Page 98 STBY Diode Mode 15.4V Open VPP/ER1 *61.4V Open VPP/ER1 *61.4V Open *64.9V Open * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 99 Label STBY Diode Mode Open VPP/ER2 *61.4V Open VPP/ER2 *61.4V Open *64.9V Open * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 100 Voltage and Diode Mode Measurements for these connectors are difficult to read. They are too close together for safe test. The pins are also protected by a layer of tape to prevent the tab from being released causing separation from the Cable and the connector. January 2009 Plasma 42PQ20...
  • Page 101 • DC Voltage and Waveform Checks • Resistance Measurements 5V Stand-By Operating Voltages Operating Voltages SMPS Supplied Developed 3.3V (2) on the Main 2.5V Board 1.8V January 2009 Plasma 42PQ20...
  • Page 102 HDMI 3 Micro. SW100 12 Mhz Tuner X501 25 Mhz Pin 19 Audio RGB/DVI P1005 LD501 Optical Audio Tuner RS232 RGB/PC Component inputs Audio In 3 Pin 1 HDMI inputs A/V Composite inputs Wired Remote S-In January 2009 Plasma 42PQ20...
  • Page 103 Main PWB Back Side (Regulator Checks) Main PWB Back Side (Regulator Checks) 1) 0.6V 2) 1.8V 3) 3.3V 1) 0V 2) 3.3V 3) 5V IC304 IC305 IC502 3) 0.2V 2) 0V 1) 0V January 2009 Plasma 42PQ20...
  • Page 104 Main PWB Tuner Check (Shield Off) Pins Exposed Main PWB Tuner Check (Shield Off) Pins Exposed VIF Pin Video Test Point SIF Pin Audio Test Point Tuner B+ (5V) MAIN Tuner Location January 2009 Plasma 42PQ20...
  • Page 105 USING COLOR BAR SIGNAL INPUT Pin 19 “Video” Signal 2.24Vp/p MAIN PWB Tuner Location Pin 16 “SIF” Pin 1 Signal Pin 12 and Pin 13 “Dig IF” Signal 450mVp/p Note: “Dig IF” Signal only when 700mVp/p receiving a Digital Channel. January 2009 Plasma 42PQ20...
  • Page 106 Main PWB Crystal X1 and X501 Check X1 (1.5V DC) / (2.4V p/p) 12Mhz Runs all the time X501 (1.5V DC) / (110mV p/p) 25Mhz X501 MAIN PWB Crystal Location Runs only at first turn on when LD501 is illuminated. LD501 January 2009 Plasma 42PQ20...
  • Page 107 Main PWB P1002 LVDS Video Signal Check Main PWB P1002 LVDS Video Signal Check USING GRAY SCALE SIGNAL INPUT Pin 11 10uSec per/Div Pin 11 2uSec per/Div Pin 1 P1002 Location Pin 18 MAIN PWB 10uSec per/Div Pin 18 2uSec per/Div 700mVp/p January 2009 Plasma 42PQ20...
  • Page 108 0.85V 1.21V 0.85V 1.27V 0.77V 1.21V 0.91V 1.22V 0.77V 1.25V 0.81V 1.24V 0.77V 1.21V 0.85V 1.24V 0.85V 1.18V 0.77V 0.58V 1.01V 3.29V 1.3V 2.81V 0.49V Resistance Readings with the PWB Disconnected. DVM in the Diode mode. January 2009 Plasma 42PQ20...
  • Page 109 03.25 Open * Pin 5 (Power Key) This pin is 0V when the button is lock “On” (In) and 5V when Locked “Off” (Out) Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 110 AC Det Open 5V Det 2.98V Vs On 3.2V Open RL On 3.73V Open AUTO M5 ON 3.26V Open Key On Open Stby5V 1.06V Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 111 Voltage and Diode Mode Measurements for the Main Board Speaker Plug P1005 CONNECTOR "Main" to "Speakers" Label Diode Mode 8.65V 2.58V 8.65V 2.58V 8.65V 2.58V 8.65V 2.58V P1005 Speaker Connector Board MAIN Location Resistance Readings with the PWB Disconnected. DVM in the Diode mode. January 2009 Plasma 42PQ20...
  • Page 112 Then remove the 2 screws from the Front IR and Power LED PWB. Remove J1connector. FRONT KEY PWB NEW: Master Power Switch Set will not function With this Mechanical” switch down in the Screw Screw open position. Screws FRONT IR and POWER LED PWB P101 FRONT KEY PWB folded back January 2009 Plasma 42PQ20...
  • Page 113 The Ft Power LED PWB includes the IR Receiver and the Intelligent Sensor. The Front POWER LED is also located on this board. FRONT POWER IR Sensor INTELLIGENT Sensor Front View To Main PWB Back View To Front Keys January 2009 Plasma 42PQ20...
  • Page 114 “Off” EYE-SDA 3.28V 2.36V (Out) Stand By 5V 5VST Open 3.3VST 5.13V 1.88V LED-R 3.3V Open LED-W 03.25 Open Open Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 115 J2 CONNECTOR “Ft LED PWB" to "Ft Keys" *STBY1 *STBY2 Diode Mode 3.29V 3.29V Open 3.29V 3.29V Open 4.38V *STBY2 Main Power Switch “IN” Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 116 The Ft Power LED PWB includes the IR Receiver and the Intelligent Sensor. The Front POWER LED is also located on this board. P101 Pin (1) To Front LED PWB Rear View Pin (1) Main Power Front View Switch Front View Back View January 2009 Plasma 42PQ20...
  • Page 117 P101 CONNECTOR “Ft Key PWB" to "Ft LED" *STBY1 *STBY2 Diode Mode 3.29V 3.29V Open 3.29V 3.29V Open Pin (1) 4.38V Open *STBY2 Main Power Switch “IN” Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. January 2009 Plasma 42PQ20...
  • Page 118 This Power Point shows a graphical representation of the 11 X 17 This Power Point shows a graphical representation of the 11 X 17 foldout page so clarity is limited. foldout page so clarity is limited. January 2009 Plasma 42PQ20...
  • Page 119 42PQ20 CIRCUIT INTERCONNECT DIAGRAM Y-SUS DRIVE WAVEFORM VR601 V Set-Up (Ramp) P813 P811 Y-SUS TP 180V M5 (9,10) Label STBY Run No Load - 5V Va (6,7) 1, 2 Z-SUS 3, 4 R502 Vs (1,2) 5, 6 7, 8 V Set-Down...
  • Page 120 Connector P1002 Configuration - indicates signal pins.
  • Page 121 End of Presentation End of Presentation This concludes the Presentation Thank You January 2009 Plasma 42PQ20...
  • Page 122 Circuit Interconnect Circuit Interconnect Blowup Y SUS Section Blowup Y SUS Section Preliminary Information 42PQ20...
  • Page 123 5V which under normal operation supplies the Control Board with 5V via the Y SUS Board. By using 5V STB, the following test will confirm Normal operation of the Control Board if that supply is missing. Preliminary Information 42PQ20...