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BIOS Setup
DRAM Clock
Use this item to configure the clock frequency of the installed DRAM.
Settings options: By SPD, 100MHz, 133MHz.
DRAM Timing
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module. Setting to By SPD enables
DRAM CAS Latency, Bank Interleave, Precharge to Active (Trp), Active
to Precharge (Tras), and Active to CMD (Trcd) automatically to be de-
termined by BIOS based on the configurations on the SPD. Selecting
Manual allows users to configure these fields manually.
DRAM CAS Latency
This setting controls the timing delay (in clock cycles) before SDRAM
starts a read command after receiving it. Setting options: 2, 2.5 (clocks).
2 (clocks) increases the system performance the most while 2.5 (clocks)
provides the most stable performance.
Bank Interleave
This field selects 2-bank or 4-bank interleave for the installed SDRAM.
Disable the function if 16MB SDRAM is installed. Setting options:
Disabled, 2 Bank, 4 Bank.
Precharge to Active (Trp)
This item allows you to control the number of SDRAM clocks used for
SDRAM parameter Trp. Trp specifies the minimum clock cycles required
for the precharge command to be transferred to the active command.
Setting options: 2T, 3T.
Active to Precharge (Tras)
This item allows you to control the number of SDRAM clocks used for
SDRAM parameters Tras. Tras specifies the minimum clock cycles re-
quired for the active command to be transferred to the precharge
command. Setting options: 5T, 6T.
Active to CMD (Trcd)
This item allows you to control the number of SDRAM clocks used for
SDRAM parameters Trcd. Trcd specifies the minimum clock cycles re-
quired for the active command to be transferred to the re-active command.
Setting options: 2T, 3T.
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