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A/ D, D/A Converter : AK4506-VS (Control U n it I C504)
• Ter m i n a l connection diagram
AINA+
1
0
AINA-
2
AINL+
3
AINL-
4
TST1
5
TST2
6
TST3
7
TST4
a
PD-AD
9
PD-DA
10
MCLK
1 1
LJR
12
SCLK
13
SOTO
14
• Ter m i n a l function
Pin No.
Name
1 / 0
1
A I N R +
I
R i g ht-c h a n n e l a n a l o g p o s i t i ve i n p ut p i n
A I N R -
2
I
R i g ht-c h a n n e l a n a l o g n e g a t ive i n p u t p i n
3
A I N L+
I
Left-c h a n n e l a n a l o g p o s i t i ve i n p u t p i n
A I N L -
4
I
Left-c h a n n e l a n a l o g n eg a t i ve i n p u t p i n
5
TST 1
I
Test p i n ( P u l l d ow n p i n )
TST2
I
O p e n or co n n ect to AG N D .
6
7
TST3
0
Test p i n
8
TST4
0
O p e n
9
P D A D
I
Power down p i n .
1 0
P D DA
I
W h e n e a c h p i n is low, t h e correspon d i n g p a rt e nters t h e power down m o d e . W h e n t h e power t u r n s o n ,
resett i n g a n d c a l i brati o n m u st b e c a r r i e d o u t . R e s ett i n g i s p e rf o r m e d b y m a k i n g both P D A D a n d P D DA l o w .
1 1
M C L K
I
M a s t e r c l o c k i n p u t p i n .
1 2
L/R
I
I n p u t/o u t p u t c h a n n e l s e l ect p i n .
1 3
S C L K
I
S e r i a l data c l o c k p i n .
1 4
S OTO
0
S e r i a l data o u t p u t p i n .
j u st i f i c at i o n . G o e s low afte r 1 6 b its a re o u t p u t .
-
1 5
D G N D
D i g i t a l u n i t g ro u n d p i n
-
1 6
V D
D i g ita l u n it power s u pp l y p i n ( + 5V)
-
1 7
V B
S i l i c o n P C B powe r s u pp l y p i n ( + 5V)
1 8
S DT I
I
S e r i a l data i n p u t p i n .
Data i s two ' s c o m p l e m e n t . T h e M S B i s o u t p u t f i rst, a n d 1 6 b i t s a re o u t p u t by r i g h t j u sti fi cat i o n .
1 9
C M O D E
I
M a s t e r c l o c k s e l ect p i n ( P u l ldown p i n )
Low : M C L K = 2 56fs, H i g h : M C L K = 3 84fs
2 0
D F S 1
I
D e e m p h a s i s freq u e n cy s e l ect p i n
2 1
D FS O
I
S u p p o rts t h ree freq u e n c i e s .
A O U T L -
2 2
0
Left-c h a n n e l a n a l o g n egative o u t p u t p i n
2 3
A O U T L +
0
Left-c h a n n e l a n a lo g p o s i t i ve o u t p u t p i n
A O U T R -
2 4
0
R i g ht-c h a n n e l a n a l o g n egative o u t p u t p i n
2 5
A O U T R +
0
R i g ht-c h a n n e l a n a l o g p o s i tive o u t p u t p i n
-
2 6
AG N D
A n a l o g g ro u n d p i n
-
2 7
VA
A n a l og power s u p p l y p i n ( + 5V)
R e f e r e n c e voltage o u t p u t p i n VA - 3 . 0V
2 8
V R E F
0
O u t p u t accord i n g to t h e VA refe r e n c e .
c o n n e cted betwe e n V R E F a n d VA.
40
SEMICONDUCTOR DATA
• Block diagram
VAEF
2a
27
VA
26
AGND
25
AO UTA+
AINL+
24
AO UTA-
AINL-
23
AOUTL+
AINA+
22
AOUTL-
AINA-
21
DFSO
20
DFS1
VAEF
19
CM ODE
1
SDTI
a
17
VB
AOUTL+
VD
16
AOUTL-
15
DGND
AOUTA+
AOUTR-
P D A D : A D C power down p i n , P D DA: DAC power down p i n
T h e f s c l o c k i s i n p u t . H i g h : Left c ha n n e l ; Low: R i g h t c h a n n e l
O n e b i t o f data i s o u t p u t at a fa l l i n g e d g e o f t h e s i g n a l at t h i s p i n .
Data i s two ' s c o m p l e m e n t . T h e M S B i s o u t p u t f i rst, a n d 1 6 b i t s a re o u t p u t b y l eft
VD
VB DGND
VA AGND
27
26
16
17
6I
Decimation
Modulator
Filter
Decimation
Fil t er
6I
lnterpolator
Modulator
6I
Modulator
lnterpolator
9
10
PD-AD PD-DA
Fu nct i o n
L o w w h e n t h e p o w e r i s down ( P D A D : Low) .
T h e 1 O µ F e l ectrolyt i c c a p a c i t o r a n d 0 . 1 µF c e ra m i c c a p a c i t o r a re
MCLK CMODE
15
1 1
19
Clock Divider
12
13 SCLK
1/0
14 SOTO
Serial
1a SDTI
Interface
ax
De-emphasis 7
Control
ax
a
21
DFSO
DFS1
LJR
5 TST1
6 TST2
TST3
TST4
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