Kenwood TS-5700 Service Manual page 16

TS-5700
Digital Control
• Overview
The TS-5700 digital control circuit has multiple chips
centered around the main CPU (IC6: M37701 OEFB),
and consists of an electronic keyer microcomputer
( IC3: UPD75004GB-746), an extended 1/0 ( IC5:
CXD10950) and DSP (IC507: ADSP2181 KS-115). A
block diagram of digital control is shown below.
IC6
MAI N CPU
IC3
S U B CPU
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Fig. Digital control section block diagram
• Address Control Circuit
The main CPU operates in the single-chip mode us­
ing the internal ROM and RAM. It transfers data from
or to the extended 1/0 and DSP through external ad­
dress and data buses.
• Encoder Circuit
The main encoder is a magnetic rotary encoder, and
the MULTI and R IT encoders are contact-type rotary
encoders.
The encoder pulses are read and processed directly
by the main CPU.
• System Reset and RAM Backup
The voltage monitor circuit (05, 08, 06, RB) moni­
tors the power supply voltage. If the voltage drops, the
circuit outputs a low signal to the INTO port of the main
CPU to stop operation. At the same time, 06 switches
the RAM backup power to a lithium battery.
If the power supply voltage becomes normal, a high
signal is input to the INTO port, the main CPU is initial­
ized b y t h e r e s e t s i g n a l g e n e r a t i o n IC ( IC 4 :
PST9121 N R ) after the time constant set b y C12 and
C13, and the operation resumes.
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CIRCUIT DESCRIPTION
IC5
EXT 1/0
IC507
DSP
• Analog Signal Input
to-digital (A / D) converter and a multiplexer (IC7 and
IC8: TC4052BF) for entering 16-channel analog signals.
Incoming analog signals are converted to digital values
by the main CPU, which are used as digital data.
• Display
parent display. The LCD is lighted with half a duty by
the LCD driver.
•
PLL unit of the TX-RX unit. The main CPU sends data
to the PLL ICs and DDS ICs according to the displayed
frequency. The PLL ICs output unlock (UNL) signals. If
one of the PLLs unlocks, the display shows that the
PLL is unlocked.
• AT Control
data (AMO) and phase difference data (PHO) to the
main CPU, controlling the serial/parallel converter in
the final unit, and changing the C capacity. The main
CPU stores the serial/parallel converter data in each
band, and whenever the frequency changes, the CPU
outputs the data automatically to optimize antenna
matching. The details of control of AMO terminal input
and PMD terminal input are given below.
IC6 7pin
INTO
15
Fig. Reset, backup circuits
The main CPU incorporates a four-channel analog­
The TS-5700 uses a positive LCD and a semi-trans­
PLL and DDS Data
The TS-5700 has two PLLs and two DDSs in the
The AT controlled by entering amplitude difference
When AMO input is low, the CO count decreases.
W hen AMO input is high, the CO count increases.
When PMD input is low, the Cl count decreases.
When PMD input is high, the Cl count increases.