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TS-570 0
•
Extended 1/0 : CXD 1 0950 (Control U n it IC5)
Term i n a l c o n n ecti o n diagram
•
Term i n a l function
P i n
N a m e
1 , 2
N C
M O
3
4
M 1
5
M 2
6
O R E N
7
V E N 1
8
R E N 1
9
R E N 2
1 0
1 1
TY P E S
1 2
TY P E 9
1 3
50WSW
1 4 - 1 7
K3 - KO
1 8
U L K
1 9
N C
2 0
P E N 1
2 1
P E N 2
2 2
D E N 1
23
D E N 2
24
B LA N K
2 5
2 6
27
L E N 1
2 8
L E N 2
2 9
L E N 3
3 0 - 3 2
I A D O - I A D 2
3 3 , 34
N C
3 5 - 3 9
I A D3 - I A D 7
4 0
4 1
42
43
44
36
SEMICONDUCTOR DATA
5 1
52
0
6 4
Port
1 / 0
P B 1
M i c ro p h o n e i n p ut switc h i n g
0
P B 2
0
M i c ro p h o n e i n p ut switc h i n g
P B 3
0
M i c ro p h o n e i n p u t switc h i n g
P B 4
0
E n a b l e
" H " : D R U -3A seria l para l l e l reg ister t h rou g h , " L" : D R U-3A seria l/para l l e l reg ister latch
" H "
: TX- RX u n it seria l/pa ra l l el reg ister thro u g h , "L"
P B 5
0
E n a b l e
" L "
: TX- RX u n i t D A C r e g i s t e r t h ro u g h , " H " : TX- RX u n i t D A C r e g i s t e r l a t c h
P B 6
0
E n a b l e
" L" : TX-RX u n it seria l/para l l e l register thro u g h , " H " : TX-RX u n it seria l/pa ral lel reg ister latch
P B 7
0
E n a b l e
Vss
G N D
P C O
I
D e s t i n a t i o n
P C 1
I
Desti n a t i o n
P C 2
I
Sett i n g c h e c k
PC3 - PC6
I
Key m a t r i x
PC7
I
State c h e c k
P D Q
0
E n a b l e
P D 1
0
E n a b l e
P D 2
0
E n a b l e
P D 3
0
E n a b l e
P D 4
0
L C D d river c ontr ol
Vss
G N D
Vdd
5V
P D 5
0
E n a b l e
P D 6
0
E n a b l e
P D 7
0
E n a b l e
D 0 - 0 2
1/0
P s e u d o b u s
0 3 - 0 7
1/0
P s e u d o b u s
C L R
I
O D E N
I
Vss
G N D
WR
I
R D
I
33
0
1 9
Deta ils
" H " :
N o r m a l m i crop h o n e i n p ut , " L " :
" H " :
Packet i n p u t , " L " : O t h e rs
" H " :
D R U -3A i n p u t , " L " : O t h e rs
50W, " H " : 1 00W
" L " :
" L" :
N ot' g e n e ra l cover i n TX, " H " : G e n e r a l cover i n TX
: W i t h o u t restrict i o n , " H " : Restriction o n 50W
" L "
" L " :
P L L u n l o c k , " H " : O t h e rs , n o r m a l
" H " :
P L L 1 register t h ro u g h , " L" :
" H " :
P L L2 reg i st e r t h r o u g h , " L" :
" H " :
D D S 1 register t h r o u g h , " L" : D D S 1 reg i st e r l a t c h
" H " :
D D S 2 register t h r o u g h , " L " : D D S 2 r e g i s t e r l a t c h
" H " : D i s p l a y g o e s off
" H " :
LC D 1 d river register t h ro u g h , " L" : LC D 1 d river register latch
" H " :
L C D 2 d river register t h ro u g h , " L" : L C D 2 d river reg i st e r l a t c h
" H " : LCD3 d river register t h ro u g h , " L" :
32
20
O t h e rs
: TX-RX u n it seria l / para l l e l reg ister latch
P L L 1 register l a t c h
P L L2 r e g i s t e r l a t c h
L C D 3 d river reg i s t e r l a t c h
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