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13.1.2. IC601 (CPU) I/O MAP
Pin No.
Pin name
Signal name
68
PA15
(nIRQ3
67
PA14
(nIRQ2
66
PA13
(nIRQ1
65
PA12
(nIRQ0
64
PA11
nRTS
62
PA10
nCTS
61
PA9
60
PA8
(nBREQ
58
PA7
(nBACK
57
PA6
(nRD
56
PA5
55
PA4
(nWR
54
PA3
(nWAIT
53
PA2
52
PA1
51
PA0
100
PB15
99
PB14
98
PB13
97
PB12
96
PB11
95
PB10
94
PB9
(TXD0
93
PB8
(RXD0
91
PB7
BID2
90
PB6
BID1
89
PB5
BID0
87
PB4
PB4
86
PB3
nFlash Busy
85
PB2
84
PB1
83
PB0
I/O
ACT
I
L
FPGA Interrupt
I
L
BELL phase detection
I
L
EMPR interrupt
I
L
DC power down recovery detection
O
L
Serial I/F for debug
I
L
Serial I/F for debug
O
Not used
O
Not used
O
Not used
O
Not used
O
Not used
O
Not used
O
Not used
O
Not used
O
Not used
O
Not used
O
Not used
Serial I/F for debug
Serial I/F for debug
I
H/L
I
H/L
Board classification judgment (Use undecided)
I
H/L
Board classification judgment (Use undecided)
I
H
H: Operation, L: Debug
I
L
Flash memory Busy
O
L
Not used
O
Not used
O
Not used
55
Description
KX-TDA6178
Remarks
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