Static Signals For Ads8568; I2C Bus For Onboard Eeprom; Figure 3-2. Static Digital Input Configuration; Figure 3-3. Eeprom For Evm Id - Texas Instruments ADS8568EVM-PDK User Manual

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Digital Interface

3.4 Static Signals for ADS8568

The ADS8568 has several static digital configuration pins. The logic state of the pin will determine the operation
of the device. For example, the PAR/SER digital pin will determine if the communication is in parallel or serial
mode. These pins are automatically controlled by the PHI digital controller when the GUI is in "hardware mode".
The logic level on these pins can be monitored using test points on J11 or as shown in
of these digital control pins also have resistors that can be used to configure the logic levels when the PHI
controller is not used.
Figure 3-2
connected to DVDD is installed. To set an input to logic low the resistor connected to GND needs to be installed.
It is important to understand that the configuration of these resistors does not matter when the PHI is used as
it will drive the logic level to whatever the GUI setting is. These digital input configuration resistors only matter
when the EVM is disconnect from the PHI and used with a different digital controller.
Figure 3-2
also shows the operation of the reset control line. This reset can be initiated by the PHI controller or
by the push button switch. Note that RESET is an active high signal so the two reset signals are applied to an
OR function so that the device will be reset if either the push button is pressed or the PHI drives the signal active
high.

3.5 I2C Bus for Onboard EEPROM

The circuit shown in
Figure 3-3
required by the ADS8568 for operation. The switch (S2) is a write protect and does not need to be changed for
EVM operation.
C59
100nF
GND
8
ADS8568EVM-PDK Evaluation Module
shows the static logic configuration. To set a pin to logic high the resistor

Figure 3-2. Static Digital Input Configuration

is used with our EVM controler (PHI), for EVM identification. This circuit is not
ID_PWR
U7
1
8
A0
VCC
2
7
A1
WP
3
6
A2
SCL
4
5
VSS
SDA
BR24G32FVT-3AGE2
GND

Figure 3-3. EEPROM for EVM ID

Copyright © 2021 Texas Instruments Incorporated
R112
10.0k
EVM_ID_WP
EVM_ID_SCL
EVM_ID_SDA
C60
100nF
GND
SBAU193E – JUNE 2011 – REVISED MAY 2021
www.ti.com
Figure
3-2. Some
S2
1
2
3
GND
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