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3 Digital Interface
As noted in
Section
1, the EVM interfaces with the PHI and communicates with the computer over the USB.
There are two devices on the EVM with which the PHI communicates: the ADS8568 ADC (over SPI) and the
EEPROM (over I2C). The EEPROM comes pre-programmed with the information required to configure and
initialize the ADS8568 platform. When the hardware is initialized, the EEPROM is no longer used.
3.1 Parallel Interface
The parallel interface signals are generated on the PHI controler and connected through J10. Each of these
signals has a 47-Ω resistor between the device and the controler to slow down the signal edges in order to
minimize signal overshoot. The digital signals can be monatored on J11 test header.
3.2 Serial Interface (SPI)
The ADS8568 ADC uses SPI serial communication in mode 2 (CPOL=1 and CPHA=0). Because the serial clock
(SCLK) frequency can be as fast as 45 MHz, the ADS8568EVM offers 47-Ω resistors between the controler
and device to aid with signal integrity. Typically, in high-speed SPI communication, fast signal edges can cause
overshoot; these 47-Ω resistors slow down the signal edges in order to minimize signal overshoot.
3.3 Connections to PHI connector
Connector J10 is used to connect the PHI digital controller PCB to the ADS8568EVM. This connector has all the
digital signals as well as the 5.5V regulated supply and the DVDD supply. The power for the two supplies is from
the USB connection. The 5.5V supply is used to generate the AVDD supply. This connector also provides I2C
signals that are used on the EEPROM identification circuit.
TP1
DVDD
DVDD
C61
10uF
GND
GND
SBAU193E – JUNE 2011 – REVISED MAY 2021
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ASLEEP
~HW_SW
CONVSTD
CONVSTC
CONVSTB
CONVSTA
~CS_~FS
~RD
RET_RD
BUSY
REFEN_~WR
~PAR_SER
RANGE_XCLK
R113
5.11
RESET1
~STBY
D5
5V
GND
CONVST_D
CONVSTD
CONVST_B
CONVSTB
ASLEEP
ASLEEP
RANGE_XCLK
RANGE/XCLK
DB1/DCIN_C
DB1_DCINC
DB3/DCIN_A
DB3_DCINA
DB5/SEL_CD
DB5_SELCD
DB7
DB9/SDI
DB9_SDI
DB11/REFBUFEN
DB11_REFBUFEN
DB13/SDO_B
DB13_SDOB
DB15/SDO_D
DB15_SDOD
~CS/~FS
~CS_~FS
REFEN_~WR
REFEN/~WR
~STBY
~STBY
Figure 3-1. PHI to ADS8568EVM connector
Copyright © 2021 Texas Instruments Incorporated
TP2
J10
5.5V
2
1
2
1
4
3
4
3
6
5
6
5
8
7
8
7
10
9
10
9
12
11
12
11
14
13
14
13
16
15
16
15
18
17
18
17
20
19
20
19
22
21
22
21
24
23
24
23
26
25
26
25
28
27
28
27
30
29
30
29
32
31
32
31
34
33
34
33
36
35
36
35
38
37
38
37
40
39
40
39
42
41
42
41
44
43
44
43
46
45
46
45
48
47
48
47
50
49
EVM_ID_WP
50
49
52
51
52
51
54
53
54
53
EVM_ID_SDA
56
55
56
55
EVM_ID_SCL
58
57
58
57
ID_PWR
60
59
60
59
MP1
MP3
GND
GND
MP2
MP4
GND
GND
QTH-030-01-L-D-A
J11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DB7
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TSW-116-07-G-D
GND
GND
Digital Interface
DB0_DCIND
GND
DB1_DCINC
DB2_DCINB
DB3_DCINA
DB4
DB5_SELCD
DB6_SELB
DB7
DB8_DCEN
DB9_SDI
DB10_SCLK
DB11_REFBUFEN
DB12_SDOA
DB13_SDOB
DB14_SDOC
DB15_SDOD
RET_SCLK
ID_PWR
GND
~HW_SW
~HW/SW
CONVSTC
CONVST_C
CONVSTA
CONVST_A
BUSY
BUSY
DB0_DCIND
DB0/DCIN_D
DB2_DCINB
DB2/DCIN_B
DB4
DB4
DB6_SELB
DB6/SEL_B
DB8_DCEN
DB8/DCEN
DB10_SCLK
DB10/SCLK
DB12_SDOA
DB12/SDO_A
DB14_SDOC
DB14/SDO_C
~RD
~RD
RESET1
RESET
~PAR_SER
~PAR/SER
ADS8568EVM-PDK Evaluation Module
7
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