Digital Baseband Processor - Panasonic EB-X300 Service Manual

5.2.2. Digital Baseband Processor

GSM Processor U101
Package 204-Ball CSPBGA
Feature
Complete single chip GSM Programmable Digital Baseband Processor divided into three main subsystems:
1. Control processor subsystem including
32-Bit MCU ARM7TDMI control processor
58.5 MHz operation at 1.8 V
1MB on-chip System SRAM Memory
2. DSP subsystem including
16-Bit Fixed Point DSP Processor
91 MIPS at 1.7 V
16K-word Data and 16K-word Program SRAM
4K-word Program Instruction Cache
Architecture supports Full Rate, Enhanced Full Rate, Half Rate, and AMR Speech Encoding / Decoding
Algorithms
3. Peripheral Subsystem including
Shared Peripheral Bus and Interface Peripherals
SYSTEM CONN.
UNIVERSAL
DSP
INTERFACE
CHANNEL
CODEC
SPI
CHANNEL
INTERFACE
EQUALISER
TEST
SPEECH
INTERFACE
CODEC
SYSTEM
SIM
SRAM
INTERFACE
MCU
DATA
INTERFACE
CONTROL
PROCESSOR
MEMORY
INTERFACE
Figure 5.6. U101 Functional Block Diagram
VOICEBAND /
BASEBAND
CODEC
INTERFACE
DISPLAY
INTERFACE
RADIO
INTERFACE
ACCESSORY
INTERFACE
KEYPAD /
BACKLIGHT
INTERFACE
USB
INTERFACE
(U101 only)
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