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5.2.2. Digital Baseband Processor
GSM processor ADI AD6525
Package 160-Ball LFBGA
Feature
Complete single chip GSM Programmable Digital Baseband Processor divided into three main subsystems:
1. Control processor subsystem including
32-Bit MCU ARM7TDMI control processor
39 MHz operation at 1.8V
1MB on-chip System SRAM Memory
2. DSP subsystem including
16-Bit Fixed-out DSP Processor
78 MIPS at 1.8V
Data and Program SRAM
Program Instruction Cache
Full rate, Enhanced full rate and Half Rate Speech Encoding / Decoding
Capable of Supporting PDC, AMR Speech Algorithms
3. Peripheral Subsystem including
Shared Peripheral Bus and Interface Peripherals
SYSTEM CONN.
UNIVERSAL
DSP
INTERFACE
CHANNEL
CODEC
TEST
CHANNEL
INTERFACE
EQUALIZER
SPEECH
SIM
CODEC
INTERFACE
SYSTEM
SRAM
DATA
INTERFACE
MCU
CONTROL
MEMORY
PROCESSOR
INTERFACE
Figure 5.6. AD6525 Functional Block Diagram
VOICEBAND /
BASEBAND
CODEC
INTERFACE
DISPLAY
INTERFACE
RADIO
INTERFACE
ACCESSORY
INTERFACE
KEYPAD /
BACKLIGHT
INTERFACE
– 5-7 –
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