Advanced Chipset Features - Intel Xeon E7500 User Manual

Advanced Chipset Features

This Setup menu controls the configuration of the chipset.
Phoenix - Award WorkstationBIOS CMOS Setup Utility
DRAM Timing Control
DRAM Timing Configure
- CAS Latency Time
- Active to Precharge Delay
- DRAM RAS# to CAS# Delay
- DRAM RAS# Precharge
System BIOS Cacheable
Video BIOS Cacheable
Delayed Transaction
Delay Prior to Thermal
DRAM Timing Control
This option when selected lets you configure DRAM timing either by
SPD or manually for items such as CAS latency time, active to precharge
delay, Active to Precharge Delay, DRAM RAS# to CAS# delay and
DRAM RAS# Precharge timing.
System BIOS Cacheable
The setting of Enabled allows caching of the system BIOS ROM at
F000h-FFFFFh, resulting in better system performance. However, if any
program writes to this memory area, a system error may result.
Video BIOS Cacheable
The Setting Enabled allows caching of the video BIOS ROM at
C0000h-F7FFFh, resulting in better video performance. However, if any
program writes to this memory area, a system error may result.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
Delay Prior to Thermal
This field activates the CPU thermal function after the systems boots for
the set number of minutes. The options are 16Min and 64Min.
Advanced Chipset Features
[Press Enter]
By SPD
1.5
7
3
3
Enabled
Enabled
Enabled
16 Min
IB900 User' s Manual
BIOS SETUP
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Menu Level
31