Receive Signalling Circuits - Motorola MCS 2000 Service Instructions Manual

7-24
Filtered Audio
(Refer to schematic page 10-29 for reference)
This signal sources receive audio or Public Address audio to a large Siren PA accessory.
The ASFIC has an audio whose output at U0200-H5 has been filtered and de-emphasized, but has
not gone through the digital volume attenuator. This signal is buffered with an op amp with a gain of
0 dB, within the ASFIC. The maximum level for this signal is 1.06 Vpp. From ASFIC U0200-H5 the
signal is AC coupled to U0201-2 by capacitor C0214. R0209 and R0208 being equal value set up the
op amp as a unity gain device, i.e. a buffer. The output at U0201-7 is then routed to J0403-11 FIL
AUD OUT. Note that any volume adjustment of the signal on this path must be done by the
accessory.
Discriminator Audio (Unfiltered)
Note that discriminator audio DISC from the ZIF, in addition to being routed to the ASFIC, is also
routed to the Hear Clear (U0250) and both option connectors J0408-5 and J0401-5 (See
Clear IC (Refer to schematic page 10-26 for reference)" on page 26
page 24 for further information).
Auxiliary RX Audio Paths
There are three auxiliary receive audio inputs that are buffered by U202 and routed to the auxiliary
receive path in the ASFIC U0200-J6. The processing for this input is identical to that of normal
received audio or it can bypass the filtering and de-emphasis. The auxiliary inputs come from the two
option connectors J0408-9 and J0401-9 and from the accessory connector J0403-15. The "voltage
mode" signal to U0400 is 9.3 V if the source for the auxiliary receive audio from J0403 is a current
source. The "voltage mode" signal is 0 V if the auxiliary receive source is a voltage source. Typically
current source mode will apply for SB9600 based devices. Note that the enable line for transmission
gate U0400-12/10 is the same line VOLTAGE MODE as that which controls the Auxiliary TX path
AUX TX IN2. The VOLTAGE MODE line is driven by Q0202 which is turned on and off by ASFIC
GCB2. In order to change the state of VOLTAGE MODE the ASFIC (U0200) must be programmed by
the SPI BUS to do so.
Secure Receive Audio
Discriminator audio, which is now coded audio, enters the ASFIC at U0200-J7. Inside the ASFIC a
path is set up to route the coded audio to a programmable 7 bit attenuator, where the signal level is
adjusted, and then out of the ASFIC at UNIV IO (U0200-B2). This path bypasses the ASFIC RX
filtering and Deemphasis. From U0200-B2 the coded audio goes to Option connectors J0401-10 /
J0408-10.
On the secure board, the coded signal is converted back to analog format, and then fed back
through (J0401-9 / J0408-9) to the Aux Rx buffer U0202. The clear audio signal is then routed to the
ASFIC pin U0200-J6; from then on it follows a path identical to conventional receive audio, where it
is filtered (300-3 kHz) and deemphasis.

Receive Signalling Circuits

(Refer to Table 7-5 for reference for the following sections).
The ASFIC (U0200) is used to filter and limit all received data. The data enters the ASFIC at U0200-
J7. Inside U0200 the data is filtered according to data type (HS or LS), then it is limited to a 0-5 V
digital level. The MDC and trunking high speed data appear at U0200-G4, where it connects to the
µP U0103-77, software decoder, and U0104-B8, hardware decoder (see SLIC description block for
further details).
December 6, 2004
Controller Section Theory of Operation: Audio and Signalling Circuits
(Refer to schematic page 10-27 for reference)
" Hear
and " Secure Receive Audio" on
68P81083C20-D