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Chapter 2
DRAM Clock
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing.
The Choices: Auto, Host CLK (default),HCLK-33M,HCLK+33M.
AGP Aperture Size
This field let you insert a timing delay between the CAS and RAS strobe signals,
used when DRAM is written to, read from, or refreshed. Fast gives faster
performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system.
The Choices: 64M (default), 32M, 16M, 8M, 4M, 128M, 256M.
AGP-4X Mode
If an insufficient number of cycles is allowed for RAS to accumulate its charge
before DRAM refresh, the refresh may be incomplete and the DRAM may fail to
retain data. Fast gives faster performance; and Slow gives more stable
performance. This field applies only when synchronous DRAM is installed in the
system.
The Choices: Enabled (default), Disabled.
AGP Driving Control
The option determines the AGP Output Buffer Drive Strength.
The Choices: Auto (default), Manual.
AGP Driving Value
The option determines the AGP Output Buffer Drive Strength.
The Choice: EC (default).
OnChip USB/USB2
This should be enabled if your system has a USB installed on the system board
and you wish to use it. Even when so equipped, if you add a higher performance
controller, you will need to disable this feature.
The Choices: Enabled (default), Disabled.
2-14
BIOS Setup
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