Block Diagram - Network Section (1/2) - Sony STR-ZA1000ES Service Manual

6-7.

BLOCK DIAGRAM - NETWORK Section (1/2) -

(ZA3000ES)
ETHERNET INTERFACE
IC7250
P6_OUTD[0]/P6_MODE[0]
P6_OUTD[1]/P6_MODE[1]
P6_OUTD[2]/P6_MODE[2]
P6_OUTD[3]/P6_VDDOS[1]
P6_OUTCLK/P6_TXC
P6_OUTEN/P6_VDDOS[0]
MDIO_CPU
J7250
11 22 P3_MDIP[0]
10 23 P3_MDIN[0]
4 25 P3_MDIP[1]
5 26 P3_MDIN[1]
3 27 P3_MDIP[2]
2 28 P3_MDIN[2]
5
8 29 P3_MDIP[3]
9 30 P3_MDIN[3]
17 34 R1_LED/P1_LED0/LED_SEL[0]
19
18 40 EE_DOUT/C3_LED/P5_LED0
20 38 EE_CLK/C1_LED/FLOW
31 13 P2_MDIP[0]
30 14 P2_MDIN[0]
24 16 P2_MDIP[1]
25 17 P2_MDIN[1]
23 18 P2_MDIP[2]
22 19 P2_MDIN[2]
6
28 20 P2_MDIP[3]
29 21 P2_MDIN[3]
37
39
38 39 EE_CS/C2_LED/P4_LED0/S_SEL
40 36 EE_DIN/C0_LED/P3_LED0/EEE_WP
51 4 P1_MDIP[0]
50 5 P1_MDIN[0]
44 7 P1_MDIP[1]
45 8 P1_MDIN[1]
43 9 P1_MDIP[2]
42 10 P1_MDIN[2]
7
48 11 P1_MDIP[3]
49 12 P1_MDIN[3]
57 33 R0_LED/P0_LED0/LED_SEL[0]
59
58
60
71 113 P0_MDIP[0]
70 114 P0_MDIN[0]
64 116 P0_MDIP[1]
65 117 P0_MDIN[1]
63 119 P0_MDIP[2]
62 120 P0_MDIN[2]
8
68 121 P0_MDIP[3]
69 122 P0_MDIN[3]
77
79
78
80
STR-ZA1000ES/ZA2000ES/ZA3000ES
93 75 P5_IND[0]/GPIO[11]
92 76 P5_IND[1]/GPIO[10]
91 77 P5_IND[2]/GPIO[9]
90 78 P5_IND[3]/GPIO[8]
P6_IND[0] 101 69 P5_OUTD[0]/P5_MODE[0]
P6_IND[1] 102 68 P5_OUTD[1]/P5_MODE[1]
P6_IND[2] 103 67 P5_OUTD[2]/P5_MODE[2]
P6_IND[3] 104 66 P5_OUTD[3]/P5_VDDOS[1]
P6_INDV 100 70 P5_OUTEN/P5_VDDOS[0]
P6_INCLK 98 71 P5_OUTCLK/P5_TXC/GPIO[14]
95 72 P5_INCLK/GPIO[13]
94 74 P5_INDV/GPIO[12]
MDIO_CPU
60
MDC_CPU
MDC_CPU 61
HUB2_INT
INTN 42
HUB2_RESET
RESETN 31
J7000
11 22 P3_MDIP[0]
10 23 P3_MDIN[0]
4 25 P3_MDIP[1]
5 26 P3_MDIN[1]
3 27 P3_MDIP[2]
2 28 P3_MDIN[2]
1
8 29 P3_MDIP[3]
9 30 P3_MDIN[3]
17 34 R1_LED/P1_LED0/LED_SEL[0]
19
18 40 EE_DOUT/C3_LED/P5_LED0
20 38 EE_CLK/C1_LED/FLOW
PoE
EACH DC 48V 15.4W
31 13 P2_MDIP[0]
30 14 P2_MDIN[0]
24 16 P2_MDIP[1]
25 17 P2_MDIN[1]
23 18 P2_MDIP[2]
22 19 P2_MDIN[2]
2
28 20 P2_MDIP[3]
29 21 P2_MDIN[3]
37
39
38 39 EE_CS/C2_LED/P4_LED0/S_SEL
40 36 EE_DIN/C0_LED/P3_LED0/EEE_WP
51 4 P1_MDIP[0]
50 5 P1_MDIN[0]
44 7 P1_MDIP[1]
45 8 P1_MDIN[1]
43 9 P1_MDIP[2]
42 10 P1_MDIN[2]
3
48 11 P1_MDIP[3]
49 12 P1_MDIN[3]
57 33 R0_LED/P0_LED0/LED_SEL[0]
59
58
60
71 113 P0_MDIP[0]
70 114 P0_MDIN[0]
64 116 P0_MDIP[1]
65 117 P0_MDIN[1]
63 119 P0_MDIP[2]
62 120 P0_MDIN[2]
4
68 121 P0_MDIP[3]
69 122 P0_MDIN[3]
77
79
78
80
XTAL_IN 126
ETHERNET INTERFACE
IC7000
P6_OUTD[0]
P6_OUTD[0]/P6_MODE[0] 93
P6_OUTD[1]
P6_OUTD[1]/P6_MODE[1] 92
P6_OUTD[2]
P6_OUTD[2]/P6_MODE[2] 91
P6_OUTD[3]
P6_OUTD[3]/P6_VDDOS[1] 90
P6_RXD0
P6_IND[0] 101
P6_RXD1
P6_IND[1] 102
P6_RXD2
P6_IND[2] 103
P6_RXD3
P6_IND[3] 104
P6_OUTEN
P6_OUTEN/P6_VDDOS[0] 94
P6_OUTCLK
P6_OUTCLK/P6_TXC 95
P6_RXCLK
P6_INCLK 98
P6_RXDV
P6_INDV 100
MDIO_CPU
MDIO_CPU 60
MDC_CPU
MDC_CPU 61
ETHEPHY_HUB1_INT
INTN 42
ETHEPHY_HUB1_RESET
RESETN 31
XTAL_IN 126
CLOCK
X7002
BUFFER
25MHz
IC7006
45 45
STR-ZA1000ES/ZA2000ES/ZA3000ES
(ZA1000ES/ZA2000ES)
J8750
ETHERNET INTERFACE
IC8750
RX+
3 5 MDI+[1] RXD[0]/CLK_CTL 8
RX–
6 6 MDI–[1] RXD[1] 9
TX+ 1 3 MDI+[0] TXD[0] 12
TX–
2 4 MDI–[0] TXD[1] 13
CRS_DV 20
REF_CLK 11
TXEN 14
D8751
MDIO 17
LED0/PHYAD[0]/
ACTIVE 18
PMEB/INTB MDC 16
INDICATOR ETHEPHY_HUB1_RESET
PHYRSTB 15
D8750
ACTIVE
19 LED1/PHYAD[1]
INDICATOR
24 CKXTAL2
X8750
25MHz
25 CKXTAL1
Ver. 1.1
P6_OUTD[0] – P6_OUTD[3], P6_RXD0 – P6_RXD3,
P6_OUTEN, P6_OUTCLK, P6_RXCLK, P6_RXDV,
MDIO_CPU, MDC_CPU, ETHEPHY_HUB1_INT,
HUB2_INT, ETHEPHY_HUB1_RESET, HUB2_RESET
>016B
(Page 46)
P6_OUTD[0]
P6_OUTD[1]
P6_RXD0
P6_RXD1
P6_OUTEN
P6_OUTCLK
P6_RXDV
MDIO_CPU
MDC_CPU