Xilinx Virtex-6 FPGA ML605 Getting Started page 37

18. Select register 0x6C, Link Capabilities Register
X-Ref Target - Figure 1-36
Virtex-6 Getting Started Guide
UG533 (v1.4) November 15, 2010
♦
Indicates the maximum number of lanes and speed supported
♦
The value 0x81 shows this is an x8 Gen1 capable device
The Link Status Register (0x70) shows the current link status
♦
This design is trained to Gen1 x8 as indicated by 0x81
Figure 1-36: Select Register 0x6C
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Getting Started with PCI Express PIO Demonstration
(Figure 1-36).
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