Hardware-Timed Single Point Acquisition Model; Maximum Hwtsp Rate Analysis; Figure 2-19. Hwtsp Data Path Model; Figure 2-20. Transfer Time And Application Time Relationship - National Instruments SC Express NI PXIe-4339 User Manual

Chapter 2 Using the Module
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Hardware-Timed Single Point Acquisition Model

The HWTSP data path is optimized for low-latency applications and is different than that which
is used in buffered acquisition model (default).
When in HWTSP mode, the filtering and sampling systems can be modeled as being decoupled,
which allows you to configure the filter and sampling rate independently.
Figure 2-19 shows the HWTSP data path model.
Analog Front End
The ADC samples the input stream and returns it to the PXI Express controller or computer at
every SampleClock signal.

Maximum HWTSP Rate Analysis

When in HWTSP, the maximum achievable acquisition rate, without missing a sample, is
affected by both the transfer and application time. Refer to Figure 2-20.
HWTSP can notify software if it cannot keep up with the acquisition rate.
Note
Refer to the Hardware-Timed Single Point Sample Mode topic in the NI-DAQmx
Help for more information.

Figure 2-20. Transfer Time and Application Time Relationship

Transfer
20 μs *
Sample
Clock
*Transfer time may vary depending on system.
**120 μs is the approximate group delay of the 2 kHz filter for input frequencies < 1 kHz
(passband of the filter).
2-28 | ni.com
.
daqhwtsp

Figure 2-19. HWTSP Data Path Model

Configurable
Low Pass Filter
Rate
= --------------------------------------------------------------------------------- -
Max
Transfer Time
Acquisition Rate Period
Application Time
A/D
1
Application Time
+
N
ni.com/info
PXI Express Controller or Computer
Wait Time (Idle)
Next Sample Filter Group Delay
120 μs **
and
Sample
Clock