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National Instruments PXIe-6569 Getting Started Manual

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PXIe-6569
Getting
Started Guide
2023-09-11

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Summary of Contents for National Instruments PXIe-6569

  • Page 1 PXIe-6569 Getting Started Guide 2023-09-11...
  • Page 2 PXIe-6569 Getting Started Guide Contents Getting Started Guide............3...

  • Page 3: Flexrio Documentation And Resources

    Getting Started Guide Note Before you begin, install and configure your chassis and controller. This document explains how to install, configure, test, and use the PXIe-6569. You can program the PXIe-6569 with the following software options. NI-FlexRIO driver software ■...
  • Page 4 PXIe-6569 Getting Started Guide Table 1. FlexRIO Documentation and Resources Document Contents PXIe-6569 Getting Started Guide (this Installation instructions ■ document) Basic programming information ■ PXIe-6569 Specifications Operating environment requirements ■ DIO specifications ■ Clocking specifications ■ Physical and mechanical specifications ■...

  • Page 5: Unpacking The Kit

    3. Unpack any other items and documentation from the kit. Store the module in the antistatic package when the module is not in use. What You Need to Get Started Kit Contents Verify that the following items are included in the PXIe-6569 kit. PXIe-6569 hardware ■ Documentation ■...

  • Page 6: Installing The Software

    PXIe-6569 Getting Started Guide Recommended Cables NI offers two lengths of optional SEARAY™ to SEARAY cables for connecting to the pins on the front panel. The following table shows the details for each. Model Name Part Number SR240M-SR240M Cable, LVDS with SE, 0.5m 787317-0R5 SR240M-SR240M Cable, LVDS with SE, 1.0m...
  • Page 7 PXIe-6569 Getting Started Guide 1. Connect the AC power source to the PXI Express chassis before installing the module. The AC power cord grounds the chassis and protects it from electrical damage while you install the module. 2. Ensure that the chassis is powered off.
  • Page 8 The following figure shows the front panel and pin layout of the Digital Data & Control (DDC) connector on the PXIe-6569. Figure 2. PXIe-6569 Front Panel Layout PXIe-6569 The following figures show the pinout of the DDC connector on the PXIe-6569 for each connector type. Clock-capable pins are denoted in bold. ni.com...
  • Page 9 PXIe-6569 Getting Started Guide Figure 3. PXIe-6569 with 32 LVDS In, 32 LVDS Out, Rows F-E FPGA Signal Connector Signal Connector Signal FPGA Signal aSeGpio(1) SE 0 SE 1 aSeGpio(3) SE_GND_TERM SE_GND_TERM To clocking CLK IN+ DI 10+* aDiffGpio_p(58)* circuitry...
  • Page 10 PXIe-6569 Getting Started Guide Figure 4. PXIe-6569 with 32 LVDS In, 32 LVDS Out, Rows D-C FPGA Signal Connector Signal Connector Signal FPGA Signal aSeGpio(5) SE 2 SE 6 aSeGpio(13) SE_GND_TERM SE_GND_TERM aSeGpio(7) SE 3 SE 7 aSeGpio(15) SE_GND_TERM SE_GND_TERM aDiffGpio_p(0)
  • Page 11 PXIe-6569 Getting Started Guide Figure 5. PXIe-6569 with 32 LVDS In, 32 LVDS Out, Rows B-A FPGA Signal Connector Signal Connector Signal FPGA Signal aSeGpio(11) SE 5 SE 4 aSeGpio(9) SE_GND_TERM SE_GND_TERM aDiffGpio_p(22) DO 10+ CLK OUT+ From clocking aDiffGpio_n(22)
  • Page 12 PXIe-6569 Getting Started Guide Figure 6. PXIe-6569 with 64 LVDS In, Rows F-E FPGA Signal Connector Signal Connector Signal FPGA Signal aSeGpio(1) SE 0 SE 1 aSeGpio(3) SE_GND_TERM SE_GND_TERM To clocking CLK IN+ DI 43+* aDiffGpio_p(58)* circuitry CLK IN- DI 43-* aDiffGpio_n(58)*...
  • Page 13 PXIe-6569 Getting Started Guide Figure 7. PXIe-6569 with 64 LVDS In, Rows D-C FPGA Signal Connector Signal SE 6 SE_GND_TERM SE 7 SE_GND_TERM DI 21+ DI 21- DI 22+ DI 22- DI 23+ DI 23- DI 24+ DI 24- DI 25+...
  • Page 14 PXIe-6569 Getting Started Guide Figure 8. PXIe-6569 with 64 LVDS In, Rows B-A FPGA Signal Connector Signal aSeGpio(11) aDiffGpio_p(22) aDiffGpio_n(22) aDiffGpio_p(26) aDiffGpio_n(26) aDiffGpio_p(24) aDiffGpio_n(24) aDiffGpio_p(25) aDiffGpio_n(25) aDiffGpio_p(27) aDiffGpio_n(27) aDiffGpio_p(31) aDiffGpio_n(31) aDiffGpio_p(32) aDiffGpio_n(32) aDiffGpio_p(40) aDiffGpio_n(40) aDiffGpio_p(36) aDiffGpio_n(36) aDiffGpio_p(45) aDiffGpio_n(45) aDiffGpio_p(39) aDiffGpio_n(39)
  • Page 15 PXIe-6569 Getting Started Guide Figure 9. PXIe-6569 with 64 LVDS Out, Rows F-E FPGA Signal Connector Signal Connector Signal FPGA Signal aSeGpio(1) SE 0 SE 1 aSeGpio(3) SE_GND_TERM SE_GND_TERM To clocking CLK IN+ DO 43+ aDiffGpio_p(58) circuitry CLK IN- DO 43- aDiffGpio_n(58)
  • Page 16 PXIe-6569 Getting Started Guide Figure 10. PXIe-6569 with 64 LVDS Out, Rows D-C FPGA Signal Connector Signal Connector Signal FPGA Signal SE 2 aSeGpio(5) SE 6 aSeGpio(13) SE_GND_TERM SE_GND_TERM aSeGpio(7) SE 3 SE 7 aSeGpio(15) SE_GND_TERM SE_GND_TERM aDiffGpio_p(0) DO 32+ DO 21+ aDiffGpio_p(4)

  • Page 17: Signal Descriptions

    RSVD PFI 1+ aDiffGpio_p(52) RSVD PFI 1- aDiffGpio_n(52) Signal Descriptions The following table describes the signal connections for the PXIe-6569. Connector Name Signal Type Description DO <0...63>+/- Data Positive and negative differential terminals for digital output channels 0 through 63.
  • Page 18 These signals should be terminated for the best single-ended signal integrity. These are terminated on the PXIe-6569 with 56 Ω to ground. NI recommends that these also be terminated on the user side of the SEARAY cable through a 56 Ω...
  • Page 19 3. Expand your Chassis tree item. MAX lists all modules installed in the chassis. Your default names may vary. Note Device Manager identifies the PXIe-6569 as the "NI FlexRIO Module (BT - KU035)" or "NI FlexRIO Module (BT - KU060)". Note If you do not see your module listed, press <F5>...
  • Page 20 PXIe-6569 Examples Examples specific to PXIe-6569 can be found in the FlexRIO with Integrated IO Project Creator. NI provides two getting started examples for each LVDS and FPGA configuration of the PXIe-6569: a basic interface and a SERDES interface. The following file names...
  • Page 21 PXIe-6569 Getting Started Guide NI Example Finder FlexRIO Example Description Show All FlexRIO with Integrated IO Hardware.vi Queries and displays a set of hardware properties from all FlexRIO with Integrated I/O devices in a chassis. Vivado Export Getting Started Ultrascale.lvproj...

  • Page 22: Component-Level Intellectual Property (Clip)

    32 or 64 LVDS Output † † The number of fixed direction LVDS input and output depends on the variant of the PXIe-6569. Component-Level Intellectual Property (CLIP) The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL IP integration. FlexRIO devices support two types of CLIP: user-defined and socketed.
  • Page 23 PXIe-6569 Getting Started Guide PXIe-6569 CLIP PXIe-6569 ships with two socketed CLIP options. These socketed CLIP options can be used as-is or can be edited to suit your application. Refer to the following table for more information about each socketed CLIP's function and the signals used in each.
  • Page 24 PXIe-6569 Getting Started Guide Socketed CLIP Signals Each LVDS configuration variant of the PXIe-6569 has a different set of signals you must use in the socketed CLIP. Some CLIP signals and data types are specific to the module variant being used. The following table lists the term used in the CLIP signals to represent each associated module variant.
  • Page 25 PXIe-6569 Getting Started Guide CLIP Signal Name Direction Data Type Description write to the SE data line. 0—Use ■ SE_Data_Rd to read the SE data line value. LVDS_PFI_Output_Ena To CLIP Boolean Provides read/write access to all low- voltage differential LVDS_PFI_Rd...
  • Page 26 PXIe-6569 Getting Started Guide CLIP Signal Name Direction Data Type Description RX Data Clock From CLIP Clock The acquisition clock for acquiring the LVDS input data. Refer Figure 1 Figure 5 for additional information. TX Data Clock From CLIP Clock...
  • Page 27 PXIe-6569 Getting Started Guide CLIP Signal Name Direction Data Type Description TX/RX Delay Increment To CLIP Boolean TX/RX Delay Increment values: 1—Increments ■ the line delay by the number of TX/RX Delay Adjust Steps when the TX/RX Delay Adjust Strobe is asserted.
  • Page 28 PXIe-6569 Getting Started Guide CLIP Signal Name Direction Data Type Description between 2.5 ps and 15 ps. Refer to the DS892 - Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics document at www.xilinx.com additional information. The FPGA delay is...
  • Page 29 Direction Data Type Description TX/RX Delay Done From CLIP Boolean Reports when an increment/decrement operation has completed. PXIe-6569 SERDES Socketed CLIP Signals CLIP Signal Name Direction Data Type Description IO Ready From CLIP Boolean Indicates successful configuration of the IO module with the current clocking mode settings.
  • Page 30 PXIe-6569 Getting Started Guide CLIP Signal Name Direction Data Type Description LVDS_PFI_Output_Ena ble values: 1—Use ■ LVDS_PFI_Wr to write to the PFI data line. 0—Use ■ LVDS_PFI_Rd to read the PFI data line value. LVDS_Data_Wr To CLIP Signals to read/write...
  • Page 31 PXIe-6569 Getting Started Guide CLIP Signal Name Direction Data Type Description LVDS output data or acquiring the input data. This clock can be sourced from the Si514 or from the LMK04832 onboard clocking ICs. Refer to Figure Figure 3, and...
  • Page 32 PXIe-6569 Getting Started Guide CLIP Signal Name Direction Data Type Description Delay Adjust Strobe is asserted. 0— ■ Decrements the line delay by the number of TX/RX Delay Adjust Steps when the TX/RX Delay Adjust Strobe is asserted. TX/RX Delay Adjust...
  • Page 33 PXIe-6569 Getting Started Guide CLIP Signal Name Direction Data Type Description www.xilinx.com additional information. The FPGA delay is restricted to the Align_Delay tap value as the lower limit and to 511 delay taps as the upper limit. Refer to the UG571 - Ultrascale...
  • Page 34 Configuring Clocks The PXIe-6569 TX/RX Data Clocks can be driven from multiple sources. The following figures show the different clock sources available on both the Basic and the SERDES CLIPs for all modules.
  • Page 35 PXIe-6569 Getting Started Guide Figure 14. All Out Clock Diagram for Basic CLIP FPGA TX Clk Selection 6569 Configure TX Clocks SampleClk Si514 Configure TxDataClk Reference Clock To LabVIEW DeviceClk InternalClk ExtClkIn Figure 15. All Out Clock Diagram for SERDES CLIP...
  • Page 36 PXIe-6569 Getting Started Guide NI Services Visit ni.com/support to find support resources including documentation, downloads, and troubleshooting and application development self-help such as tutorials and examples. Visit ni.com/services to learn about NI service offerings such as calibration options, repair, and replacement.