Xilinx System Generator V2.1 Reference Manual page 78

Xilinx System Generator v2.1 Reference Guide
Figure 3-52: FFT Timing Characteristics
For 16-point FFTs, the block is always in the "ready for data" state and output frames
are delivered continuously. Thus, there are no stall periods (stall = stall_0 = 0), and the
frame variable of the timing diagram defaults to 16 sample periods. There is,
however, a pipeline delay (i.e., it takes some time for the first output frame to appear)
with frame_0 = 84 sample periods.
Xilinx LogiCORE
The block always uses the Xilinx LogiCORE fft V1.0 (Virtex) or FFT V2.0 (Virtex-II).
The number of points supported are N=16, 64, 256, or 1024. The 64, 256, and 1024
point FFTs contain external memories implemented with the LogiCORE Dual Port
Block Memory V3.2. The number of memory blocks (either 1, 2, or 3) determines the
timing characteristics and size of the implementation. The FFT LogiCOREs support
only 16-bit data, although in simulation, the System Generator FFT block supports
other data sizes.
The Core datasheets can be found on your local disk at:
For Virtex:
%XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft\doc\c_ff
t1024_v1_0.pdf
%XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft\doc\c_ff
t16_v1_0.pdf
%XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft\doc\c_ff
t256_v1_0.pdf
%XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft\doc\c_ff
t64_v1_0.pdf
For Virtex-II:
%XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft_v2_0\doc
\vfft1024v2.pdf
%XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft_v2_0\doc
\vfft16v2.pdf
%XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft_v2_0\doc
\vfft256v2.pdf
%XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft_v2_0\doc
\vfft64v2.pdf
78
Single Memory
stall_0 = 275
64-point stall = 275
frame_0 = 277
frame = 339
stall_0 = 1074
256-point stall = 1074
frame_0 = 1076
frame = 1330
stall_0 = 5170
1024-point stall = 5170
frame_0 = 5172
frame = 6194
Double Memory Triple Memory
stall_0 = 146 stall_0 = 0
stall = 128
frame_0 = 276 frame_0 = 406
frame = 192 frame = 192
stall_0 = 789 stall_0 = 0
stall = 768
frame_0 = 1075 frame_0 = 1589
frame = 1024 frame = 768
stall_0 = 4117 stall_0 = 0
stall = 4096
frame_0 = 5171 frame_0 = 8246
frame = 5120 frame = 4096
Xilinx Development System
stall = 0
stall = 0
stall = 0