Installed System Generator Directory; Using Black Boxes - Xilinx System Generator V2.1 Reference Manual

Xilinx System Generator v2.1 Reference Guide

Installed System Generator directory

The installer will create the following directory structure on your PC:
These directories contain the following:

Using Black Boxes

There are times when a design must include subsystems that cannot be realized with
Xilinx blocks. For example, the design might require a FIR filter whose capabilities
differ from those in the filter supplied in the Xilinx Blockset. Black boxes provide a
way to include such subsystems in designs otherwise built from Xilinx blocks. To add
a black box to a design, do the following:
A Black Box Example
The directory: /xilinx/sysgen/examples/black_box, ordinarily stored in
$MATLAB/toolbox) contains an example showing how to use black boxes.
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xilinx/
sysgen/
bin
examples
help
scripts
vhdl
bin - This is the location of all system files. You should not add, delete, or change
files in this subdirectory.
examples - This subdirectory contains examples that show how to run the
software. This subdirectory also includes demonstration projects which show
proper use of some of the Xilinx blocks.
help - The System Generator documentation (.pdf files, viewable in Adobe
Acrobat) is located here.
scripts - This directory contains auxiliary Perl scripts which are used by the
System Generator. These scripts are described in Chapter 6 of this document.
vhdl - This directory contains a library of core VHDL files used to construct your
System Generator design.
Implement the subsystem (your black box) in Simulink. The subsystem can
contain any combination of Xilinx and non-Xilinx blocks.
Place the Xilinx Black Box token at the top level sheet of the subsystem. This
indicates to System Generator that the user will provide the VHDL or Verilog
HDL necessary to implement that subsystem.
Double-click on the token to open the Black Box block parameters dialog box.
Enter the information that describes the black box.
You must manually enter your VHDL or Verilog HDL black box files into your
downstream software tools project after you run the System Generator code-
generation step.
Xilinx Development System