Viterbi Decoder - Xilinx System Generator V2.1 Reference Manual

Xilinx inc. portable generator user manual
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Xilinx System Generator v2.1 Reference Guide
Other parameters used by this block are described in the Common Parameters section
of the previous chapter.
The RS Encoder block cannot be placed in an enabled subsystem in System Generator
v2.1. See the Enabled Subsystems section (within the MATLAB I/O library
documentation) explanation for more details.
Latency
The RS Encoder has a 6 sample period latency for CCSDS code specification and a 4
sample period latency for all other specifications.
Xilinx LogiCore
The RS Encoder block uses Xilinx LogiCORE RS Encoder v2.0.
The Core datasheet can be found on your local disk at:
%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\rs_encoder_v2_0\
doc\rs_encoder.pdf
This is a licensed core, available for purchase on the Xilinx web site at:
http://www.xilinx.com/ipcenter/reed_solomon

Viterbi Decoder

length of the trace through the trellis is determined from the traceback length
parameter.
The Viterbi Decoder has a lower error rate when given optimal convolution codes. On
the Convolutional Encoder, the convolution codes are used to select which bits in the
constraint register are XORed to generate the encoded output. The convolution codes
must match those on the corresponding convolutional encoder. When using sub-
optimal codes, the opposite path has the same cost as the desired path in the Viterbi
trellis and decoding errors will result. The following table provides a list of optimal
codes. The constraint length is inferred from the length of the convolution code.
Constraint
length
68
The Xilinx Viterbi Decoder block is used for decoding
convolutionally encoded data. The first step in decoding is to
assess the cost of the incoming data against all possible data input
combinations. Either the Hamming or Euclidean metric is used to
determine the cost. The cost determines the distance to each state
in the Viterbi trellis. The second and final decoding step is to trace
backwards through the trellis and determine the optimal path. The
Optimal convolution codes for
decoding 1/2 rate encoders
3
111,101
4
111,1011
5
11111,11011
6
101111, 110101
7
1001111,1010111
8
11101111, 10011011
Optimal convolution codes for
decoding 1/3 rate encoders
111,111,101
111,1011,1101
11111,11011,10101
101111, 110101,111001
1001111,1010111,1101101
11101111, 10011011, 10101001
Xilinx Development System

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