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Xilinx System Generator v2.1 Reference Guide
Concat .................................................................................................................30
Constant ..............................................................................................................31
Convert ................................................................................................................31
Counter ................................................................................................................32
Delay ...................................................................................................................35
Down Sample ......................................................................................................36
Get Valid Bit .........................................................................................................37
Mux ......................................................................................................................38
Parallel to Serial ..................................................................................................39
Register ...............................................................................................................40
Reinterpret ...........................................................................................................42
Serial to Parallel ..................................................................................................43
Set Valid Bit .........................................................................................................45
Slice .....................................................................................................................45
Sync .....................................................................................................................47
Up Sample ...........................................................................................................50
Communication .........................................................................................................52
Convolutional Encoder ........................................................................................52
Depuncture ..........................................................................................................54
Interleaver Deinterleaver .....................................................................................55
Puncture ..............................................................................................................58
RS Decoder .........................................................................................................59
RS Encoder .........................................................................................................63
Viterbi Decoder ....................................................................................................68
DSP ..........................................................................................................................70
CIC ......................................................................................................................70
DDS .....................................................................................................................73
FFT ......................................................................................................................75
FIR .......................................................................................................................79
Math ..........................................................................................................................81
Accumulator .........................................................................................................81
AddSub ................................................................................................................83
CMult ...................................................................................................................84
Inverter ................................................................................................................85
Logical .................................................................................................................86
Mult ......................................................................................................................88
Negate .................................................................................................................90
Relational .............................................................................................................90
Scale ....................................................................................................................92
Shift .....................................................................................................................92
SineCosine ..........................................................................................................93
Threshold .............................................................................................................95
MATLAB I/O ..............................................................................................................96
Gateway Blocks ...................................................................................................96
Enabled Subsystems ...........................................................................................96
Gateway In ...........................................................................................................97
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Xilinx Development System
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