Xilinx System Generator V2.1 Reference Manual page 41

Block Interface
The block has one input port for the data and an optional input reset port. The initial
output value is specified by the user in the block parameters dialog box (below). Data
presented at the input will appear at the output after one sample period. Upon reset,
the register assumes the initial value specified in the parameters dialog box.
The Register block differs from the Xilinx Delay block by providing an optional reset
port and a user specifiable initial value.
Block Parameters Dialog Box
The block parameters dialog box can be invoked by double-clicking the icon in your
Simulink model.
Figure 3-16: Register block parameters dialog box
Parameters specific to the block are:
Other parameters used by this block are explained in the Common Parameters section
of the previous chapter.
The Register block is implemented as a synthesizable VHDL module. It does not use a
Xilinx LogiCORE.
Basic Elements
Initial Value: specifies the initial value in the register.
Quantization (of Initital Value): specifies desired quantization effect;
one on Round or Truncate.
Overflow Effect (of Initital Value): specifies desired overflow effect;
Wrap, Saturate, or Flag as Error.
Register Only Valid Data: when checked, only valid values are registered.
Extra logic is added when this option is selected, thus decreasing system
performance.
Use Reset Port: when checked, the optional reset port is activated.
Use Enable Port: when checked, the optional clock enable port is activated.
Xilinx Blocks
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