Black Box - Xilinx System Generator V2.1 Reference Manual

Xilinx System Generator v2.1 Reference Guide

Black Box

treated as a black box. You may want to build a model out of non-Xilinx blocks for an
HDL representation of functionality that you want to turn into a Simulink model.
To create a black box in the System Generator, you must supply both a Simulink
model and a corresponding HDL file.
Incorporating mixed language black boxes
System Generator creates VHDL for the Xilinx blocks in your design. But if you
include a black box that is written in Verilog HDL, System Generator will produce a
mixed language project.
A VHDL black box and a Verilog black box share the same interface, as is seen below
in the description of the block parameters. You must specify the VHDL/Verilog
design unit name, and specify types, names, and values of generics or parameters.
You must also specify how many clocks the black box has and how these clocks
should be associated with ports.
In addition, you must specify whether you are inserting a VHDL black box or a
Verilog black box by choosing the appropriate language in the HDL Language option
on the Black Box block parameter dialog. System Generator will generate a
corresponding wrapper in the chosen language.
Block Parameters Dialog Box
The Black Box block parameters dialog box encapsulates the design information
necessary for the compiler to create the correct instantiation interfaces. This black box
support allows you to abstract commonly used control signals and ports, and then
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The Xilinx Black Box token enables you to instantiate your own
specialized functions in your model, and subsequently into a generated
design. Like the System Generator token, the Black Box token can be
placed in any Simulink subsystem, identifying the subsystem as a black
box. If you choose to include functionality in your Simulink model that
does not exist in the current blockset, any Simulink subsystem can be
Xilinx Development System