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Xilinx System
Generator v2.1
Simulink
User Guide
Xilinx Blockset
Reference Guide
Introduction
Xilinx Blockset Overview
Xilinx Blocks
System Generator Software Features
Using the Xilinx Software
Auxiliary Files
for
Printed in U.S.A.
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Summary of Contents

  • Page 1

    Xilinx System Generator v2.1 Simulink User Guide Xilinx Blockset Reference Guide — Introduction Xilinx Blockset Overview Xilinx Blocks System Generator Software Features Using the Xilinx Software Auxiliary Files Printed in U.S.A.

  • Page 2

    Chapter 3, Xilinx Blocks, describes the details of each block, including options, and use of Xilinx LogiCOREs . This chapter also tells where to find descriptions of the cores on your computer. Chapter 4, System Generator Software Features, describes the System Generator software and gives tips for using it to create efficient hardware designs.

  • Page 3

    This page contains a link to the Xilinx Xtreme DSP solutions page. Technical Tips Latest news, design tips, and patch information for the Xilinx design environment. http://support.xilinx.com/xlnx/xil_tt_home.jsp Tutorials Tutorials covering Xilinx ISE 4.1i design flows, from design entry to verification and debugging. http://support.xilinx.com/support/techsup/tutorials/ tutorials4.htm Documentation Xilinx Software Manuals online.

  • Page 4

    Xilinx System Generator v2.1 Reference Guide Conventions This document uses the following conventions. An example illustrates each convention. Typographical The following conventions are used for all System Generator documents. Courier font (a fixed-width font) indicates messages, prompts, menu pick items, and dialog box entries that the system displays.

  • Page 5: Table Of Contents

    Instantiating Xilinx Blocks within a Simulink Model ...16 The Block Parameters Dialog Box ...16 The Nature of Signals in the Xilinx Blockset ...16 Use of Xilinx Smart-IP Cores by the System Generator ...18 Licensed Cores ...18 Xilinx LogiCORE Versions ...19 Common Options in Block Parameters Dialog Box ...19...

  • Page 6: Table Of Contents

    Xilinx System Generator v2.1 Reference Guide Concat ...30 Constant ...31 Convert ...31 Counter ...32 Delay ...35 Down Sample ...36 Get Valid Bit ...37 Mux ...38 Parallel to Serial ...39 Register ...40 Reinterpret ...42 Serial to Parallel ...43 Set Valid Bit ...45 Slice ...45...

  • Page 7: Table Of Contents

    Important Issues ...136 Files automatically created by System Generator ...137 Chapter 5 Using the Xilinx Software Xilinx ISE 4.1i Project Navigator ...139 Opening a System Generator project ...139 Customizing your System Generator project ...139 Implementing your design ...140 Simulating using ModelSim within the Project Navigator ...141 Using an EDIF software flow ...143...

  • Page 8: Industry And Product Overview

    Xilinx System Generator v2.1 Reference Guide Introduction This chapter describes the basic concepts and tools of the System Generator v2.1. This chapter contains the following sections. Industry and Product Overview System Generator System Level Modeling with System Generator The System Generator Design Flow...

  • Page 9: System Generator, System Level Modeling With System Generator

    constructs for simulation, its synthesizable subset is far too restrictive for system design. System Generator is a software tool for modeling and designing FPGA-based DSP systems in Simulink. The tool presents a high level abstract view of a DSP system, yet nevertheless automatically maps the system to a faithful hardware implementation.

  • Page 10: The System Generator Design Flow

    The System Generator Design Flow Simulink provides a graphical environment for creating and modeling dynamical systems. System Generator consists of a Simulink library called the Xilinx Blockset, and software to translate a Simulink model into a hardware realization of the model.

  • Page 11

    END ENTITY Figure 1-1: System Generator design flow diagram The Xilinx Blockset is accessible in the Simulink library browser, and elements can be freely combined with other Simulink elements. Only those subsystems denoted as Xilinx black boxes, and blocks and subsystems consisting of blocks from the Xilinx Blockset are translated by System Generator into a hardware realization.

  • Page 12: Arithmetic Data Types

    Xilinx System Generator v2.1 Reference Guide Simulink hierarchy into a hierarchical VHDL netlist. In addition, System Generator creates the necessary command files to create the IP block netlists using CORE Generator , invokes CORE Generator, and creates project and script files for HDL simulation, synthesis, technology mapping, placement, routing, and bit stream generation.

  • Page 13: Hardware Handshaking, Multirate Systems

    Generator then propagates signal types and precisions as appropriate. The automatically chosen type is the least expensive that preserves full precision. Translations from signed to unsigned and vice versa are automatic as well. System Generator also allows designs to contain elements that cannot be realized in hardware, but assist development and debugging.

  • Page 14: Bit-true And Cycle-true Modeling, Automatic Testbench Generation

    Xilinx System Generator v2.1 Reference Guide Bit-True and Cycle-True Modeling System Generator produces a hardware implementation that is bit and cycle true to the system level simulation. We define the term bit and cycle true at the boundaries of the design. The boundaries of a design in System Generator are specified by the presence of Gateway In and Gateway Out blocks.

  • Page 15: What Is A Xilinx Block

    The System Generator is able to generate an FPGA implementation consisting of RTF VHDL and Xilinx Smart-IP Cores from a Simulink subsystem built from the Xilinx Blockset. The overall design, including test environment, may consist of arbitrary Simulink blocks. However, the...

  • Page 16: Instantiating Xilinx Blocks Within A Simulink Model, The Block Parameters Dialog Box

    Generator will convert to hardware are those from the Xilinx Blockset. The Block Parameters Dialog Box Most Xilinx blocks have parameters that can be configured. The typical block has a dialog box with several common parameters (common to most blocks in the blockset) and some specific parameters (specific to the particular block only).

  • Page 17

    filled up, or it may denote bursty outputs, as with an FFT. Blocks in the Xilinx Blockset can use this valid bit signal to determine what to do with the input data. Some of the Xilinx blocks, for example, the storage blocks and the FFT, use the valid bit to determine when to store input data.

  • Page 18: Use Of Xilinx Smart-ip Cores By The System Generator, Licensed Cores

    LogiCORE, System Generator automatically maps the block onto the synthesizable module. For example, the Xilinx Negate block generates a LogiCORE if you specify input of up to 256 bits, but for more than 256 bits the block is realized in synthesizable VHDL.

  • Page 19: Xilinx Logicore Versions, Common Options In Block Parameters Dialog Box

    Xilinx LogiCORE Versions The Xilinx LogiCORE the System Generator) used in Xilinx System Generator v2.1 are listed below. Xilinx Block Accumulator Addressable Shift Register Adder/Subtractor Counter Constant Multiplier Convolutional Encoder Dual Port Ram FIFO FIR Filter Interleaver/ Deinterleaver Inverter Logical...

  • Page 20: Arithmetic Type, Implement With Xilinx Smart-ip Core (if Possible), Generate Core, Latency

    VHDL. If you do not select this checkbox, the software will instead create synthesizable VHDL. Selecting this option does not guarantee that a Xilinx LogiCORE will be used. If the parameters for your block are such that a core cannot be generated, synthesizable VHDL will be generated instead.

  • Page 21: Precision, Override With Doubles

    fixed point arithmetic. Most blocks give you the option of choosing the precision, i.e. the number of bits and binary point position. By default, the output of Xilinx blocks is full precision; that is, sufficient precision to represent the result without error. Most blocks have a User-Defined precision option that fixes the number of total and fractional bits.

  • Page 22: Sample Period

    You can easily identify which blocks are currently set to Override with Doubles. When this option is set, affected Xilinx blocks are displayed in gray rather than the normal blue or yellow. Sample Period Data streams are processed at a specific sample rate as they flow through Simulink.

  • Page 23: Basic Elements, System Generator

    Xilinx Blocks This chapter describes each Xilinx block in detail. Xilinx blocks are grouped within six categories, also shown in the Simulink library browser. They are: Basic Elements Communication Math MATLAB I/O Memory State Machine Basic Elements The Xilinx Basic Elements library includes the standard building blocks for digital designs.

  • Page 24

    Specify where the output files (VHDL, cores, and project files) will be written. It is suggested that you create a separate directory (away from your Simulink model files) to generate your files in order to keep your Xilinx project files and Simulink model files directories organized separately.

  • Page 25

    Simulink simulation. This is particularly useful during design and debugging. The Override with Doubles directive from a System Generator token is applied to all Xilinx blocks on the same sheet and recursively through all subsystems on the sheet. Additional System Generator tokens can be inserted into the subsystems to selectively mask this effect.

  • Page 26: Addressable Shift Register

    The Xilinx Addressable Shift Register block is a variable-length shift register (or delay chain). This block differs from the Xilinx Delay block in that the amount of latency experienced by data from input to block output is variable and depends on the address value.

  • Page 27

    Xilinx LogiCORE The block always uses the Xilinx LogiCORE Ram-based Shift Register V5.0. When the Generate Core parameter is checked, the Use Placement Information parameter provides the option of generating the core as a Relationally Placed Macro (RPM) or as unplaced logic.

  • Page 28: Black Box

    Simulink subsystem can be treated as a black box. You may want to build a model out of non-Xilinx blocks for an HDL representation of functionality that you want to turn into a Simulink model.

  • Page 29

    Xilinx Blocks infer them in the generated VHDL. The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-3: Black Box block parameters dialog box Parameters specified as cell arrays (generic or parameter names, types, and values) permit several methods for entering data.

  • Page 30: Concat

    Parameters used by this block are explained in the Common Parameters section of the previous chapter. The Concat block does not use a Xilinx LogiCORE. The Xilinx Concat block performs a concatenation of two bit vectors represented by unsigned integer numbers, i.e. two unsigned numbers with binary points at position zero.

  • Page 31: Constant, Convert

    Constant The Xilinx Constant block generates a constant. This block is similar to the Simulink constant block, but can be used to drive the inputs on Xilinx blocks. Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

  • Page 32: Counter

    The output for an up counter is calculated as follows: The down counter calculation replaces addition by subtraction. The Xilinx Counter block implements an up or down counter. It can be configured to step between the starting and ending values, provided the increment evenly divides the difference between the starting and ending values.

  • Page 33

    The block can be configured as a free running up or down counter by selecting the Provide Reset Pin option on the block parameters dialog box. In this case, the block has a reset input port in addition to its output port. Xilinx Blocks...

  • Page 34

    Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The Counter block parameters dialog box is invoked by double-clicking the block icon. Figure 3-8: Counter block parameters dialog box Parameters specific to the block are: Number of Bits: specifies the number of bits in the counter.

  • Page 35: Delay

    Other parameters used by this block are explained in the Common Parameters section of the previous chapter. The Delay block does not use a Xilinx LogiCORE, but is efficiently mapped to utilize the SRL16 feature of Xilinx devices. Basic Elements The Xilinx Delay block is a delay line (also called a shift register) of configurable length, allowing you to add latency to your design.

  • Page 36: Down Sample

    Figure 3-11: Down sample circuit behavior The Xilinx Down Sample block reduces the sample rate at the point where the block is placed in your design. The input signal is under- sampled so that every nth input sample is presented at the output and held.

  • Page 37: Get Valid Bit

    There are no parameters for this block. Basic Elements The Xilinx Get Valid Bit element sets its output to 1 when its input is a valid data value. The output is set to 0 otherwise. In the Xilinx Blockset, every data sample that flows through the model is accompanied by a handshake validation signal.

  • Page 38

    Xilinx LogiCORE The block uses the Xilinx LogiCORE Bus Multiplexer V5.0. When the Generate Core parameter is checked, the Use Placement Information for Core parameter provides the option of generating the core as a Relationally Placed Macro (RPM) or as unplaced logic.

  • Page 39: Parallel To Serial

    The Parallel to Serial block takes an input word and splits it into N time multiplexed output words where N equals the number of input bits/ number of output bits. The order of the output is either least significant bit first or most significant bit first. Xilinx Blocks...

  • Page 40: Register

    Other parameters used by this block are explained in the Common Parameters section of the previous chapter. The Parallel to Serial block does not use a Xilinx LogiCORE. Register The Xilinx Register block models a D flip flop-based register, having latency of one sample period.

  • Page 41

    Upon reset, the register assumes the initial value specified in the parameters dialog box. The Register block differs from the Xilinx Delay block by providing an optional reset port and a user specifiable initial value.

  • Page 42: Reinterpret

    -2.0 (1110.00 in binary, two’s complement) would be translated into an output of 56 (111000 in binary). This block can be particularly useful in applications that combine it with the Xilinx Slice block or the Xilinx Concat block. To illustrate the block’s use, consider the...

  • Page 43: Serial To Parallel

    Output Binary Point: The position to which the output’s binary point is to be forced. The supplied value must be an integer between zero and the number of bits in the input (inclusive). This block does not use any hardware resources. The block does not use a Xilinx LogiCORE. Serial to Parallel...

  • Page 44

    Xilinx System Generator v2.1 Reference Guide The following waveform illustrates the block’s behavior: Figure 3-18: Example of Serial to Parallel behavior This example illustrates the case where the input width is 1, output width is 4, word size is 1 bit, and the block is configured for most significant word first.

  • Page 45: Set Valid Bit, Slice

    In the Xilinx Blockset, every data sample that flows through the model is accompanied by a handshake validation signal. In the corresponding The Xilinx Slice block allows you to slice off a sequence of bits from your input data and create a new data value. This value is presented as the output from the block.

  • Page 46

    Xilinx System Generator v2.1 Reference Guide only the first three fractional bits. The following diagram illustrates how to extract all but the top 16 and bottom 8 bits of the input. Figure 3-21: Slice block operation Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

  • Page 47: Sync

    Basic Elements The Xilinx Sync Block synchronizes two to four channels of data so that their first valid data samples appear aligned in time with the outputs. The input of each channel is passed through a delay line and then presented at the output port for that channel.

  • Page 48

    The following diagram illustrates the operation of this block. Figure 3-23: Sync block use This diagram shows a two-channel Xilinx Sync Block connected to two signal sources, with one producing a sawtooth wave and the other a sine wave. The sawtooth generator is able to produce its output much more quickly than the sine generator.

  • Page 49

    Moreover, should a pipeline stage be either added to or removed from the sine wave generator, the pipeline balancing delay line would have to be re-tuned. The Xilinx Sync block allows such balancing operations to be automated. Figure 3-25: Design with delay rather than Sync block The Sync block can be configured to have up to four channels and to add latency to all...

  • Page 50: Up Sample

    The timing diagram shown below demonstrates the circuit's behavior. It is important to notice that this circuit has a combinatorial path The Xilinx Up Sample block increases the sample rate at the point where the block is placed in your design. The input signal is over- sampled so that every nth input sample is presented at the output, or presented once with (n-1) zeroes interspersed.

  • Page 51

    (copied) during the extra sample times. If this checkbox is not selected, the additional samples are zero. Other parameters used by this block are explained in the Common Parameters section of the previous chapter. The Up Sample block does not use a Xilinx LogiCORE. Basic Elements Xilinx Blocks...

  • Page 52: Communication, Convolutional Encoder

    UFix1_0. The size of the output port, dout, is determined by the output rate. The port will be either type UFix2_0 or UFix3_0. The Xilinx Convolutional Encoder block implements an encoder for convolutional codes. Commonly used in tandem with a...

  • Page 53

    System Generator v2.1. See the Enabled Subsystems section (within the MATLAB I/O library documentation) explanation for more details. Xilinx LogiCORE The block always uses the Xilinx LogiCORE: Convolutional Encoder v1.0. The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\convolution_v1_0 \doc\convolution.pdf...

  • Page 54: Depuncture

    UFixK_0 where K equals the length of insert string x (the length of the depuncture code ). The Xilinx Depuncture block can be used to decode a range of punctured convolution codes. The following diagram illustrates an application of this block to implement soft decision Viterbi decoding of punctured convolution codes.

  • Page 55: Interleaver Deinterleaver

    Block Parameters Dialog Box The Xilinx depuncture block can be configured using its Block Parameters dialog box. Figure 3-33: Depuncture block parameters dialog box Parameters specific to the Xilinx Puncture block are: Depuncture Code: specifies the depuncture pattern for inserting the string to the input.

  • Page 56

    Xilinx System Generator v2.1 Reference Guide Figure 3-34: Forney convolutional interleaver with a constant difference between consecutive branches When the block is in deinterleaver mode, the input data sampled on the DIN port is multiplexed into and out of (synchronized) commutator arms. Branch 0 will have a shift register of length ( Branch ( -1) shall have a shift register length of zero.

  • Page 57

    Memory Type: Automatically chosen, block RAM or distributed RAM Other parameters used by this block are described in the Common Parameters section of the previous chapter. Xilinx LogiCORE The block always uses the Xilinx LogiCORE: Interleaver/Deinterleaver v1.1. Communication Xilinx Blocks...

  • Page 58: Puncture

    The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\sid_v1_1\doc\sid .pdf This is a licensed core, available for purchase on the Xilinx web site at: http://www.xilinx.com/ipcenter/interleaver Puncture the puncture code) and outputs data of type UFixK_0 (where K is equal to the number of ones in the puncture code).

  • Page 59: Rs Decoder

    Block Parameters Dialog Box The Xilinx puncture block can be configured using its Block Parameters dialog box. Figure 3-38: Puncture block parameters dialog box Parameters specific to the Xilinx Puncture block are: Puncture Code: specifies the puncture pattern for removing the bits from the input.

  • Page 60

    Block Interface The Xilinx RS Decoder Block has two input (din, rst) and four output (dout, info, fail, err_cnt) ports. The RS Decoder block also has two optional input ports (start, erase) and one optional output port (erase_cnt).

  • Page 61

    Systems) standard full length and shortened RS code. DVB: implements DVB (Digital Video Broadcasting) standard (204, 188) shortened RS code. IESS-308 (126): implements IESS-308 (INTELSAT Earth Station Standard) specification (126, 112) shortened RS code. IESS-308 (194): implements IESS-308 specification (194, 178) shortened RS code. Communication Xilinx Blocks...

  • Page 62

    Xilinx System Generator v2.1 Reference Guide IESS-308 (208): implements IESS-308 specification (208, 192) shortened RS code. IESS-308 (219): implements IESS-308 specification (219, 201) shortened RS code. IESS-308 (225): implements IESS-308 specification (225, 205) shortened RS code. Symbol Width: specifies the symbol width for the RS code. The RS decoder supports symbol width from 3 to 12.

  • Page 63: Rs Encoder

    The RS Decoder block uses Xilinx LogiCORE: RS Decoder v2.0. The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\rs_decoder_v2_0\ doc\rs_decoder.pdf This is a licensed core, available for purchase on the Xilinx web site at: http://www.xilinx.com/ipcenter/reed_solomon RS Encoder Figure 3-41: Example of a system using Reed-Solomon codes The Reed-Solomon encoder takes a block of digital data and adds extra, redundant bits.

  • Page 64

    Xilinx System Generator v2.1 Reference Guide type of errors that can be corrected depends on the characteristics of the Reed- Solomon code. Reed-Solomon codes are a subset of BCH (Bose, Chaudhuri, and Hocquenghem) codes and are linear block codes. A Reed-Solomon code is specified as RS(n,k) with s- bit symbols.

  • Page 65

    Block Interface The Xilinx RS Encoder block has two inputs (din, rst) and three output (dout, info and rfd) ports. The RS Encoder block also has optional start and bypass input ports. Figure 3-43: Reed-Solomon Encoder icons, including optional ports The port descriptions are: din: carries the input information symbols of the RS code.

  • Page 66

    Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The RS Encoder block can be configured using its Block Parameters dialog box. Figure 3-44: Reed-Solomon Encoder block parameters dialog box Parameters specific to the RS Encoder block are: Code Specification: specifies the type of RS Encoder desired. The choices are: Custom: allows you to set all the block parameters.

  • Page 67

    + x + 1 – – hx GS – - 1). Xilinx Blocks Array Representation [1 0 1 1] [1 0 0 1 1] [1 0 0 0 1 1] [1 0 0 0 0 1 1] [1 0 0 0 1 0 0 1]...

  • Page 68: Viterbi Decoder

    The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\rs_encoder_v2_0\ doc\rs_encoder.pdf This is a licensed core, available for purchase on the Xilinx web site at: http://www.xilinx.com/ipcenter/reed_solomon Viterbi Decoder length of the trace through the trellis is determined from the traceback length parameter.

  • Page 69

    Use of hard coding requires input data to be 1 bit wide. Soft coding requires the input data to be 3 to 8 bits (inclusive). The output Xilinx Blocks Optimal convolution codes for decoding 1/3 rate encoders 111101101, 110011011, 100100111...

  • Page 70

    The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\viterbi_v1_0\doc \viterbi.pdf This is a licensed core, available for purchase on the Xilinx web site at: http://www.xilinx.com/ipcenter/viterbi This library contains blocks that implement Digital Signal Processing (DSP) specific functions.

  • Page 71

    Xilinx Blocks Block Interface The CIC Block has one input and one output port. The input port can be between 1 and 32 bits (inclusive). The two basic building blocks of a CIC filter are the integrator and the comb. A single integrator is a single-pole IIR filter with a transfer function of:...

  • Page 72

    See the Enabled Subsystems section (within the MATLAB I/O library documentation) explanation for more details. Xilinx LogiCORE The CIC block always uses the Xilinx LogiCORE: CIC v1.0. The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\cic_v1_0\doc\ C_CIC_V1_0.pdf...

  • Page 73

    To understand how to use the DDS block, it is necessary to understand how the block is implemented in hardware, as the block parameters are defined in terms of the DDS implementation as a Xilinx LogiCORE. The figure below shows a high-level view of the core. The input phase increment accumulator.

  • Page 74

    Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-49: DDS block parameters dialog box Parameters specific to the DDS block are: Function: specifies the block output to be sine, cosine, or both.

  • Page 75

    Other parameters used by this block are described in the Common Parameters section of the previous chapter. Xilinx LogiCORE The DDS block always uses the Xilinx LogiCORE DDS v4.0. The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\dds_v4_0\doc\dds .pdf...

  • Page 76

    N-th root of unity. The FFT block accepts as input a stream of complex data represented as a pair of Xilinx fixed point data and computes successive DFTs of nonoverlapping frames of N data samples. Block Interface...

  • Page 77

    FFT and the memory usage mode selected. For triple memory configurations, the timing numbers are specified in terms of the output data sample period.) Figure 3-51: FFT Timing Diagram Xilinx Blocks...

  • Page 78

    = 84 sample periods. Xilinx LogiCORE The block always uses the Xilinx LogiCORE fft V1.0 (Virtex) or FFT V2.0 (Virtex-II). The number of points supported are N=16, 64, 256, or 1024. The 64, 256, and 1024 point FFTs contain external memories implemented with the LogiCORE Dual Port Block Memory V3.2.

  • Page 79

    N-tap filter is defined by N filter coefficients (or taps) h(0), h(1), ...,h(n- 1). Here each h(i) is a Xilinx fixed point number. The filter block accepts a stream of Xilinx fixed point data samples x(0), x(1), ..., and at time n computes the output: –...

  • Page 80

    filter taps. You can choose one of these: inferred from coefficients, none, symmetric, negative symmetric, half band, and interpolate fir. Number of bits per coefficient: Xilinx fixed point parameter. Binary point for coefficients: Xilinx fixed point parameter. Coefficient arithmetic type: Xilinx fixed point parameter.

  • Page 81: Math, Accumulator

    Xilinx LogiCORE The block always uses the Xilinx LogiCORE Distributed Arithmetic FIR Filter V6.0. The Simulink model operates on a sample in/sample out basis, but the core has the capability of using serial arithmetic by overclocking. Although this adds latency, it has the benefit of reducing the hardware required for the filter.

  • Page 82

    Other parameters used by this block are explained in the Common Parameters section of the previous chapter. Xilinx LogiCORE The block always uses the Xilinx LogiCORE Accumulator V5.0. The data width must be between 1 and 258, inclusive. The Core datasheet can be found on your local disk at:...

  • Page 83: Addsub

    Other parameters used by this block are explained in the Common Parameters section of the previous chapter. Xilinx LogiCORE If the Implement with Xilinx Smart-IP Core checkbox is selected on the parameters dialog box, and if the output width is in the range of 1 to 256, the block Math The Xilinx AddSub block implements an adder/subtractor.

  • Page 84: Cmult

    Xilinx System Generator v2.1 Reference Guide uses the Xilinx LogiCORE Adder Subtractor V5.0. Otherwise, the block is implemented as a synthesizable VHDL module. The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\addsub.pdf CMult The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

  • Page 85: Inverter

    Other parameters used by this block are explained in the Common Parameters section of the previous chapter. Xilinx LogiCORE The block always uses the Xilinx LogiCORE Multiply Generator V4.0. The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\mult_gen_v4_0\do c\mult_gen.pdf...

  • Page 86: Logical

    Reference Guide. Xilinx LogiCORE The Inverter block uses the Xilinx LogiCORE Bus Gate V5.0 if the Implement with Xilinx Smart-IP Core parameter is checked and the input data width is between 1 and 64, inclusive. Otherwise, the block is implemented as a synthesizable VHDL module.

  • Page 87

    Xilinx LogiCORE The Logical block uses the Xilinx LogiCORE Bus Gate V5.0 if the Implement with Xilinx Smart-IP Core parameter is checked and the input data width is between 1 and 64, inclusive. Otherwise, the block is implemented as a synthesizable VHDL module.

  • Page 88: Mult

    Simulink model. Figure 3-59: Mult block parameters dialog box - parallel type The Xilinx Mult block implements a multiplier. It computes the product of the data on its two input ports, producing the result on its output port. The block supports a size-performance tradeoff in its implementation.

  • Page 89

    Other parameters used by this block are explained in the Common Parameters section of the previous chapter. Xilinx LogiCORE The Mult block always uses Xilinx LogiCORE: Multiply Generator V4.0. The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\mult_gen_v4_0\do c\mult_gen.pdf...

  • Page 90: Negate, Relational

    Xilinx LogiCORE If the Implement with Xilinx Smart-IP Core checkbox is selected and the input width is between 1 and 256, inclusive, the block uses the Xilinx LogiCORE Twos Complementer V5.0. Otherwise, the block is implemented as a synthesizable VHDL module.

  • Page 91

    Xilinx LogiCORE The block uses the Xilinx LogiCORE: Comparator V5.0 if the Implement with Xilinx Smart-IP Core checkbox is selected and the output widths to the block are between 1 and 64, inclusive. Otherwise, the block is implemented as a synthesizable VHDL module.

  • Page 92: Scale, Shift

    The Scale block does not use a Xilinx LogiCORE. Shift The Xilinx Scale block scales its input by a power of two. The power can be either positive or negative. The block has one input and one output. The scale operation has the effect of moving the binary point without changing the bits in the container.

  • Page 93: Sinecosine

    Other parameters used by this block are explained in the Common Parameters section of the previous chapter. The Shift block does not use a Xilinx LogiCORE. SineCosine full period to reduce memory size). The input signal must be an unsigned integer.

  • Page 94

    Xilinx LogiCORE The block always uses the Xilinx LogiCORE Sine/Cosine Look-Up Table V3.0. The input and output width determine whether the ROM stores a full or quarter wave. The distributed memory case stores a full wave for table depths less than or equal to...

  • Page 95: Threshold

    Greater than 4 Greater than 8 The Xilinx Threshold block tests the sign of the input number. If the input number is negative, the output of the block is -1; otherwise, the output is 1. The output is a signed fixed point integer that is 2 bits long.

  • Page 96: Matlab I/o, Gateway Blocks, Enabled Subsystems

    The System Generator infers clock circuitry in its hardware implementation from the sample periods defined in the Simulink model for the Xilinx blocks. This circuitry includes clock (CLK), clock enable (CE), and clear (CLR) ports on registers and Xilinx Xilinx Development System...

  • Page 97: Gateway In

    Enable Adapter block, found in the Xilinx blockset’s MATLAB I/O library. An example of this requirement is shown in the figure below. This shows an address generation model for a MAC-based FIR filter.

  • Page 98

    Xilinx System Generator v2.1 Reference Guide The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-68: Gateway In block parameters dialog box Parameters specific to the Gateway In block are: IOB Timing Constraint: In hardware, a Gateway In is realized as a set of input/output buffers (IOBs).

  • Page 99: Gateway Out

    MATLAB I/O The Xilinx Gateway Out block is output from the Xilinx FPGA part of your Simulink design. It converts System Generator fixed point data to Simulink double precision. According to its configuration, it can either define an output port for the top level of the HDL design...

  • Page 100

    Xilinx System Generator v2.1 Reference Guide The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-69: Gateway Out block parameters dialog box Parameters specific to the Gateway Out block are: IOB Timing Constraint: In hardware, a Gateway Out is realized as a set of input/output buffers (IOBs).

  • Page 101: Quantization Error Blocks, Display

    fixed point signal. You may view the quantization error by sending the output of the block into a display or scope. This is the Simulink Display block, linked into the Xilinx Blockset’s MATLAB I/O section as a convenience. It is presented as output to the Sample Time display (described next).

  • Page 102: Memory, Dual Port Ram

    Xilinx System Generator v2.1 Reference Guide Memory This section contains Xilinx blocks that use Xilinx memory LogiCOREs. Dual Port RAM Block Interface The block has two independent sets of ports for simultaneous reading and writing. Each port set has one output port and three input ports for address, input data, and write enable (WE).

  • Page 103

    This means that the output can be the old value which corresponds to Read After Write. Figure 3-70: Illustration of write modes Memory Xilinx Blocks...

  • Page 104

    Xilinx System Generator v2.1 Reference Guide Virtex, Virtex-E and Spartan-II families support only Read After Write. Virtex-II supports all modes. Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

  • Page 105

    Xilinx LogiCORE The block uses the Xilinx LogiCORE: Dual Port Block Memory v3.2 The address width must be equal to where d denotes the memory depth. The tables below show the widths that are acceptable for each depth. Table: Maximum Width for Various Depth Ranges (Virtex/Virtex-E)

  • Page 106: Fifo

    FIFO is at least 50% full. Given two bits of precision, the possible output values are 0.00, 0.25, 0.50 and 0.75. The Xilinx FIFO block implements a First-In-First-Out memory queue. Values presented at the module’s data-input port is written to the next available empty memory location when the write-enable input is one.

  • Page 107

    Other parameters used by this block are described in the Common Parameters section of the previous chapter. Xilinx LogiCORE The block always uses the Xilinx LogiCORE: Synchronous FIFO V3.0. The core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\sync_fifo_v3_0\d oc\sync_fifo.pdf...

  • Page 108

    Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-73: ROM block parameters dialog box Parameters specific to this block are: Depth: specifies the number of words stored; must be a positive integer.

  • Page 109

    Other parameters used by this block are explained in the Common Parameters section of the previous chapter. Xilinx LogiCORE The block always uses a Xilinx LogiCORE: Single Port Block Memory V3.2 or Distributed Memory V5.0. For the block memory, the address width must be equal to where d denotes the memory depth.

  • Page 110: Single Port Ram

    For block memory, the behavior of the output port depends on the write mode selected. When the WE is 0, the output port has the value at the location specified by the address line. The Xilinx Single Port RAM block implements a random access memory (RAM). Xilinx Development System...

  • Page 111

    During a write operation (WE asserted), the data presented to the data input is stored in memory at the location selected by the address input. During a write cycle, the user can configure the behavior of the data out port A to one of the following choices: Memory Xilinx Blocks...

  • Page 112

    Xilinx System Generator v2.1 Reference Guide Read After Write Read Before Write No Read On Write The write modes can be described with the help of the figure shown below. In the figure the memory has been set to an initial value of 5 and the address bit is specified as 4.

  • Page 113

    Xilinx LogiCORE The block always uses a Xilinx LogiCORE Single Port Block Memory V3.2 or Distributed Memory V5.0. For the block memory, the address width must be equal to where d denotes the memory depth. The tables below show the width that is acceptable for each depth.

  • Page 114: State Machine, Mealy State Machine

    RAMs, resulting in a very fast and efficient implementation. For example, a state machine with 8 states, 1 input, and 2 outputs that are registered can be realized with a single block RAM that runs at more than 150 MHz in a Xilinx Virtex device. Mealy State Machine Figure 3-76: Mealy State Machine block diagram The block is configured by providing next state and output matrices.

  • Page 115

    Xilinx Blocks stream of bits. The state transition diagram and equivalent transition table are shown below. Figure 3-77: Mealy State Machine example transition diagram and table The table lists the next state and output that result from the current state and input.

  • Page 116: Moore State Machine

    Virtex family, the maximum number of states supported is 4K and for Virtex-II it is 64K. Xilinx LogiCORE This block uses Version 3.2 of the Xilinx Single Port Block Memory LogiCORE and Version 5.0 of the Xilinx Distributed RAM LogiCORE. The Core datasheet for the Single Port Block Memory may be found locally at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemsp_v3_2\do c\sp_block_mem.pdf...

  • Page 117

    Xilinx Blocks A block diagram of this type of state machine is shown below: Figure 3-80: Moore State Machine block diagram The block is configured by providing a next state matrix and an output array. They are defined by the state machine’s next state/output table. For example, consider the problem of designing a state machine to recognize the pattern ’1011’...

  • Page 118

    Xilinx System Generator v2.1 Reference Guide The Next State Matrix and the and Output Array are composed in the following way: Figure 3-82: Construction of Next State and Output matrices The rows of the matrices correspond to the current state. The next state matrix has one column for each input value.

  • Page 119: Registered Mealy State Machine

    Xilinx LogiCORE This block uses Version 3.2 of the Xilinx Single Port Block Memory LogiCORE and Version 5.0 of the Xilinx Distributed RAM LogiCORE. The Core datasheet for the Single Port Block Memory may be found locally at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemsp_v3_2\do c\sp_block_mem.pdf...

  • Page 120

    Xilinx System Generator v2.1 Reference Guide stream of bits. The state transition diagram and equivalent transition table are shown below. Figure 3-85: Registered Mealy State Machine example transition diagram and table The table lists the next state and output that result from the current state and input.

  • Page 121

    Xilinx Blocks The Registered Mealy State Machine block is configured with next state and output matrices obtained from the next state/output table discussed above. These matrices are constructed as follows: Figure 3-86: Construction of Next State and Output matrices The rows of the matrices correspond to the current state, and columns correspond to the input value.

  • Page 122

    The block RAM width and depth limitations are described in the online help for the Single Port RAM block. Xilinx LogiCORE This block uses Version 3.2 of the Xilinx Single Port Block Memory LogiCORE. The Core datasheet for the Single Port Block Memory may be found locally at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemsp_v3_2\do c\sp_block_mem.pdf...

  • Page 123: Registered Moore State Machine

    ’1011’ within a serial State Machine The Xilinx Registered Moore State Machine block implements a state machine whose output depends only on the current state. This block is like the Moore State Machine block, except that its output logic is registered.

  • Page 124

    Xilinx System Generator v2.1 Reference Guide stream of bits. The state transition diagram and next state/output table are shown below. Figure 3-89: Registered Moore State Machine example transition diagram and table The table lists the next state and output that result from the current state and input.

  • Page 125

    Simulink model: Figure 3-91: Registered Moore State Machine block parameters dialog box The next state logic, state register, is implemented using the Xilinx Block RAM LogiCORE. A separate Block RAM LogiCORE is used to implement the output logic and output register.

  • Page 126

    Number of States Xilinx LogiCORE This block uses Version 3.2 of the Xilinx Single Port Block Memory LogiCORE. The block RAM width and depth limitations are described in the core datasheet for the Single Port Block Memory, which may be found locally at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemsp_v3_2\do c\sp_block_mem.pdf...

  • Page 127: Using The System Generator Installer, Uninstalling Previous System Generator Directories

    The System Generator installer is now contained in a single MATLAB file: setup.dll. Download SysgenInstall_v2_1.exe from the Xilinx web site and execute it. This extracts setup.dll and README.txt to a temporary directory. Since setup.dll is a MATLAB file, you will need to install the software from within MATLAB. Open the MATLAB console, then change directories (cd) to the temporary directory where you extracted setup.dll.

  • Page 128: Using Black Boxes

    Xilinx blocks. For example, the design might require a FIR filter whose capabilities differ from those in the filter supplied in the Xilinx Blockset. Black boxes provide a way to include such subsystems in designs otherwise built from Xilinx blocks. To add a black box to a design, do the following: Implement the subsystem (your black box) in Simulink.

  • Page 129: Black Box Window

    - a MATLAB function for reversing bit order bit_reverse.vhd - VHDL code for reversing bit order. This file is the actual black box that must be passed to the Xilinx implementation tools. It imitates the behavior of the MATLAB function.

  • Page 130: Use Of Mixed Language Projects, Incorporating Mixed Language Black Boxes

    The System Generator’s code-generation software creates VHDL code from the system representation (Xilinx Blockset portion) of your design. Even though VHDL is the only choice for the generated output language, System Generator supports mixed language designs in two ways: You can incorporate Verilog into a System Generator design as a black box.

  • Page 131

    enter information describing clocks, parameter names, types and values as appropriate. Figure 4-2: Black Box block parameters dialog box Creating mixed language synthesis and simulation projects The following describes how to synthesize mixed language designs using Synplify and Leonardo Spectrum synthesis compilers, and how to test using the ModelSim simulator.

  • Page 132: Tips For Creating A High Performance Design

    Up and down samplers have combinational feedthroughs. Whenever possible, place a register on the output of a sample rate converter. The Xilinx blocks Up Sample and Down Sample (in the Xilinx Blockset Basic Elements library) provide more information.

  • Page 133: Using The System Generator Constraints Files, System Clock Period, Multicycle Path Constraints

    Leonardo or Synplify project files that System Generator creates, thus making it easy to correlate between the Timing Analyzer report and the Simulink model. For more information refer to Xilinx Application note 406 at http://www.xilinx.com/xapp/xapp406.pdf Using the System Generator Constraints Files When System Generator transforms a design into HDL, it also writes a constraints file...

  • Page 134: Iob Timing And Placement Constraints, Example For Showing Constraints Use

    Xilinx System Generator v2.1 Reference Guide The division of the design into parts, and the speed at which each part must run, are specified in the constraints file using multicycle path constraints. The example below shows how this is done.

  • Page 135

    The ce2_group contains the blocks operating at twice the system period, i.e., the input register and the up sampler. Here are the corresponding constraints. # ce2_group and inner group constraint INST "InReg" TNM = "ce2_group"; INST "Up_Sample" TNM = "ce2_group"; TIMESPEC "TS_ce2_group_to_ce2_group"...

  • Page 136: Important Issues

    (1) It is important to note that design hierarchy is used to specify the assignment of blocks to clock groups. The project files created by System Generator for XST (Xilinx Synthesis Technology), Synplify and Leonardo Spectrum tell the synthesis tools to preserve this hierarchy.

  • Page 137: Files Automatically Created By System Generator

    When a System Generator project is created, the software produces design VHDL and cores from the Xilinx CORE Generator. In addition, many other project files are created. Following is a description of the files you can expect to find in your System Generator generated project directory.

  • Page 138

    Xilinx System Generator v2.1 Reference Guide sysgen.log - log file. xlRunScripts.log - log file showing status of post-processing scripts run by System Generator. Xilinx Development System...

  • Page 139: Xilinx Ise 4.1i Project Navigator, Opening A System Generator Project, Customizing Your System Generator Project

    During code generation, the System Generator creates several project files for use in Xilinx and partner software tools. One is for the Xilinx 4.1i ISE Project Navigator tool. By opening this project file, you can import your System Generator design into the Project Navigator, and from there, you can synthesize, simulate, and implement the design in the Xilinx 4.1i software tools environment.

  • Page 140: Implementing Your Design

    Implementing your design You have many options within Project Navigator for working on your project. You can open any of the Xilinx software tools such as the Floorplanner, Constraints Editor, report viewers, etc. To implement your design, you can simply instruct Project Navigator to run your design all the way from synthesis to bitstream.

  • Page 141: Simulating Using Modelsim Within The Project Navigator

    files that were produced on the way to bitstream creation. For example, if you wish to see how your design was placed on the Xilinx FPGA, you can select the FloorPlanner view underneath the Place & Route option in the Process window.

  • Page 142

    Xilinx System Generator v2.1 Reference Guide pn_posttranslate.do - this file will run a simulation on the output of the Xilinx translation (ngdbuild) step, the first step of implementation. pn_postmap.do - to run a simulation after your design has been mapped. This file also includes a back-annotated simulation on the post-mapped design.

  • Page 143: Using An Edif Software Flow, Simulation, Compiling Your Ip

    Xilinx Edition of ModelSim (MXE). You may run your simulations from the standalone ModelSim tool, or you may associate it with the Xilinx 4.1i ISE Project Navigator, and run your simulations from within Project Navigator as part of the full software implementation flow.

  • Page 144: Associating Modelsim With Ise 4.1i Project Navigator

    Unzip these MXE libraries into your MXE installed directory (usually $MXE/ xilinx/vhdl/xilinxcorelib). This is the location where MXE expects to find your Xilinx compiled libraries, so you do not need to make any changes to your modelsim.ini file. This file should point to the correct installed location.

  • Page 145: Xilinx Software Tools Resources

    After you make this association, your System Generator projects within Project Navigator will automatically use this ModelSim simulator. Figure 5-10: Processes associated with System Generator testbench in Project Navigator Xilinx software tools resources Documentation, tutorials, and other Xilinx software tools resources can be found online at http://support.xilinx.com/support/techsup/tutorials/ tutorials4.htm http://toolbox.xilinx.com/docsan/xilinx4/...

  • Page 146: Demonstration Designs

    Figure 6-1: Opening MATLAB demonstration designs This will launch the MATLAB Demos window, from where you can browse to the System Generator demonstration designs, under the Xilinx Blockset category.. Figure 6-2: MATLAB Demos window with Xilinx Blockset chosen Chapter 6...

  • Page 147: Perl Scripts

    As a convenience, several Perl scripts are delivered together with the System Generator software. These Perl scripts generate project files or scripts that support Xilinx ISE 4.1i Project Navigator, as well as Xilinx partner simulation and synthesis tools. These Perl scripts are run automatically by System Generator. We advise that you not change these scripts.

  • Page 148

    Xilinx System Generator v2.1 Reference Guide Xilinx Development System...

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