Hard Drive Circuitry - Sony XM-1502SX Training Manual

CD Start Up
When power is applied to the Acc and Battery input, CD ROM IC8 and CPU IC1010 (CPU not shown in Figure 4-
8) are reset. IC1010 requests a check of all active storage devices using Chip Select (CS) and data bus lines.
Five seconds after power is applied, the CD section is checked. That is when the CS and Interrupt (reply) pulses
are active as shown in the waveform of Figure 4-13. The scope used here is a 100MHz digital scope. On an
analog scope the Interrupt signals (channel 1) are easy to lock but the CS signals (channel 2) require you to
touch up the trigger level control.
Figure 4-13 - CD Communications 10
seconds after applying Power
Signal Location
1 INTRQ CN7/pin
(Interrupt to 10
CPU as
IC1010) next
CN7
2 ZCS1FX CN7/pin 4
(Chip select same
from CPU R116 next
IC1010 to to CN7.
IC8).
Time base = 20 usec/division

Hard Drive Circuitry

The hard drive is located under the main (middle) board and uses the circuitry on the main board to play music.
Communications must take place before audio is produced. Both communications and audio processing for
music use the circuitry on the main board. See Figure 4-8.
Communications
At start up when power is applied, CPU IC1010 outputs clock (CkI0 pin 162), chip select (XCS4 pin 100), (not
shown) and instruction on the address and data bus to CPU Interface IC2003. Interface IC2003 translates the
information and communicates with the hard drive using chip select XCS0, XCS1 and the ATAPI data bus.
Table of contents information from the hard drive is returned to the CPU IC1010 for display using the same route
(ATAPI data bus, IC2003, main address/data bus, IC1010).
Music Playback
In a similar manner to the communications path when a song has been selected, CPU IC1010 instructs the hard
drive to assemble the pieces of the song selected. As the hard drive assembles the song, data is output the
ATAPI bus into the CPU Interface
Voltage
p-p
4.5Vp-p
same (2V/div)
R122
to
5Vp-p
as (2V/div)
47
4. Car Music Storage Unit