General Operation
4.2.
Response Time
The response time is the time that elapses from the change of an input until setting of an output of
the IP 265.
In the preceding section, we already mentioned the program execution time of the FPGA. For the
assessment of the response time of the IP 265, additional delays must be considered when using
the 24 V inputs and 24 V outputs.
The response time consists of the following three components:
•
Input delay
•
Program execution period
•
Output delay
Input
24 V
circuit
inputs
5 V
differential
inputs
Expansion
inputs
Input delay
Figure 4-3. Time Diagram - Response Time of IP 265
4-4
default
De-
bounc-
ing
config.
Program execution time
Response time of IP 265
FPGA
IP 265
Pro-
gram
IP 265
Output
24 V
circuit
outputs
Expan-
sion
outputs
Output delay
Time t
EWA 4NEB 812 6130-02a