Texas Instruments TMS320 Series User Manual page 42

SCI/BLIN Control Registers
Table 6. SCI Global Control Register (SCIGCR1) Field Descriptions (continued)
Bit Field
6 LIN MODE
5 CLK_MASTER
4 STOP
3 PARITY
2 PARITY ENA
1 TIMING MODE
42 Local Interconnect Network (LIN) Module
Value Description
LIN mode
This bit controls the module mode of operation.
0 LIN mode is disabled; SCI compatibility mode is enabled.
1 LIN mode is enabled; SCI compatibility mode is disabled.
SCI internal clock enable or LIN Master/Slave configuration.
In the SCI mode, this bit enables the clock to the SCI module. In LIN mode, this bit determines
whether a LIN node is a slave or master.
SCI-compatible mode
0 Reserved.
1 Enable clock to the SCI module.
LIN mode
0 The node is in slave mode.
1 The node is in master mode.
SCI number of stop bits.
This bit is effective in SCI-compatible mode only.
0 One stop bit is used.
1 Two stop bits are used.
Note: The receiver checks for only one stop bit. However in idle-line mode, the receiver waits until
the end of the second stop bit (if STOP = 1) to begin checking for an idle period.
SCI parity odd/even selection.
SCI-Compatible mode only. If the PARITY ENA bit (SCIGCR1.2) is set, PARITY designates odd or
even parity.
0 Odd parity is used.
1 Even parity is used.
Note: The parity bit is calculated based on the data bits in each frame and the address bit (in
address-bit mode). The start and stop fields in the frame are not included in the parity calculation.
Note: For odd parity, the SCI transmits and expects to receive a value in the parity bit that makes
odd the total number of bits in the frame with the value of 1.
For even parity, the SCI transmits and expects to receive a value in the parity bit that makes even
the total number of bits in the frame with the value of 1.
Parity enable.
Enables or disables the parity function. Compatible or buffered SCI mode:
SCI compatibility or buffered SCI mode
0 Parity disabled; no parity bit is generated during transmission or is expected during reception
1 Parity enabled. A parity bit is generated during transmission and is expected during reception
LIN mode
0 ID-parity verification is disabled.
1 ID-parity verification is enabled.
SCI timing mode bit.
This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. It
configures the SCI for asynchronous operation.
0 Reserved.
1 Must be set to 1 when module is configured for SCI operation
Preliminary
SPRUGE2A – May 2009 – Revised June 2009
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