Panasonic PT-D10000U Service Manual page 79

15.5. Signal Processing (2/2) (PT-DW10000)
Signal Processing (2/2) (for PT-DW10000*)
A-P.C.Board
1
POCLK
IC2005
IP CONVERTER,
2
SCALING
128M
DDR-SDRAM
IC2006, IC2007
4
3
IC2638 IC2635
INVERTER I/O
IC2615
CPUGOOD_OUT
AN_CPUH CPUHS
4 CPU
CPUPOWERGOOD
IC2604, IC2605
IC2506
IIC
CPU_AD_ETC
SELECTORS
4
5
IC2515 IC2514
INVERTER INVERTER
A6 FH1
IC5001
FPGA
IC5101
CPLD
IIC_SEL0-3
IC2505
I/O
SELECTOR
S1
A2
FH-Module
P_PWRGOOD
PC-Module
PC4
IC5106
FH8
R
FH9
R
FPGA
FH6
IC5102
SRAM
G
IC5103
FLASH
ROM
FH7
G
IC5105
FH4
CLOCK
GENERATOR
150 MHz
X5102
B
IC5104
CLOCK
GENERATOR
200 MHz
FH5
X5103
B
79
PT-D10000U / PT-D10000E / PT-DW10000U / PT-DW10000E
IC4007
IC4008, IC4009
LVDS
RLDRAM
FR1 RECEIVER
REBOOTZ
IC4002
RESET FPGA
RLDRAM
TERM. REG
IC4003
FR3
IC4005
DMD
SAT_PROG_B
REGULATOR
FR-Module
IC4006
IC4307
IC4308, IC4309
LVDS
RLDRAM
FG1 RECEIVER
REBOOTZ
IC4302
RESET FPGA
RLDRAM
TERM. REG
IC4303
FG3
IC4305
DMD
SAT_PROG_B
REGULATOR
FG-Module
IC4306
IC4307
IC4308, IC4309
LVDS
RLDRAM
RECEIVER
FG1
REBOOTZ
IC4302
RESET FPGA
RLDRAM
TERM. REG
IC4303
FG3
IC4305
DMD
SAT_PROG_B
REGULATOR
FG-Module
IC4306
Q4002
RLDRAM
RESET
0.95
1080p
DMD
Q4302
RLDRAM
RESET
0.95
1080p
DMD
Q4302
RLDRAM
RESET
0.95
1080p
DMD