Texas Instruments TMS320C645x DSP User Manual page 40

EMAC Functional Architecture
2.7.2 MDIO Module Operational Overview
The MDIO module implements the 802.3 serial management interface to simultaneously interrogate and
control up to two Ethernet PHYs, using a shared two-wired bus. It separately performs auto-detection and
records the current link status of up to 32 PHYs, polling all 32 MDIO addresses.
Application software uses the MDIO module to configure the auto-negotiation parameters of the primary
PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the
EMAC. Up to two Ethernet PHYs can be directly controlled and queried. The Media Independent Interface
addresses of these two PHY devices are specified in the PHYADRMON fields of the USERPHYSELn
register. The module can be programmed to trigger a CPU interrupt on a PHY link change event by setting
the LINKINTENB bit in USERPHYSELn. Reads and writes to registers in these PHY devices are
performed using the USERACCESSn register.
The MDIO module powers up in an idle state until it is enabled by setting the ENABLE bit in the
CONTROL register. This also configures the MDIO clock divider and preamble mode selection. The MDIO
preamble is enabled by default, but it can be disabled if none of the connected PHYs require it.
Once the MDIO module is enabled, the MDIO interface state machine continuously polls the PHY link
status (by reading the generic PHY Status register) of all possible 32 PHY addresses and records the
results in the ALIVE and LINK registers. The corresponding bit for each PHY (0-31) is set in the ALIVE
register if the PHY responded to the read request. The corresponding bit is set in the LINK register if the
PHY responded and also is currently linked. In addition, any PHY register read transactions initiated by
the application software using the USERACCESSn register cause the ALIVE register to be updated.
The USERPHYSELn register is used to track the link status of any two of the 32 possible PHY addresses.
Changes in the link status of the two monitored PHYs sets the appropriate bit in the LINKINTRAW and
LINKINTMASKED registers, if they are enabled by the LINKINTENB bit in USERPHYSELn.
While the MDIO module is enabled, the host can issue a read or write transaction over the management
interface using the DATA, PHYADR, REGADR, and WRITE bits in the USERACCESSn register. When
the application sets the GO bit in USERACCESSn, the MDIO module begins the transaction without any
further intervention from the CPU. Upon completion, the MDIO module clears the GO bit and sets the
USERINTRAW[0-1] bit in the USERINTRAW register corresponding to the USERACCESSn used. The
corresponding USERINTMASKED bit in the USERINTMASKED register may also be set, depending on
the mask setting configured in the USERINTMASKSET and USERINTMASKCLEAR registers.
A round-robin arbitration scheme schedules transactions that may be queued using both USERACCESS0
and USERACCESS1. The application software must verify the status of the GO bit in USERACCESSn
before initiating a new transaction to ensure that the previous transaction has completed. The application
software can use the ACK bit in USERACCESSn to determine the status of a read transaction.
2.7.2.1 Initializing the MDIO Module
To have the application software or device driver initialize the MDIO device, perform the following:
1. Configure the PREAMBLE and CLKDIV bits in the CONTROL register.
2. Enable the MDIO module by setting the ENABLE bit in the CONTROL register.
3. The ALIVE register can be read after a delay to determine which PHYs responded, and the LINK
register can determine which of those (if any) already have a link.
4. Set up the appropriate PHY addresses in the USERPHYSELn register, and set the LINKINTENB bit to
enable a link change event interrupt if desirable.
5. If an interrupt on a general MDIO register access is desired, set the corresponding bit in the
USERINTMASKSET register to use the USERACCESSn register. If only one PHY is to be used, the
application software can set up one of the USERACCESSn registers to trigger a completion interrupt.
The other register is not set up.
40 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
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SPRU975B – August 2006
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