JVC SR-DVM70AG Schematic Diagrams page 37

VIDEO BLOCK DIAGRAM (2)
TO_DV_DUB_Y
Y
1
TO_DV_DUB_C
C
2
REAR1_YV_IN
Y
3
REAR2_YV_IN Y
4
DV_V_OUT
5
I2C_CLK2
6
I2C_DATA2
7
DV_Y_OUT
Y
8
REAR2_C_IN C
9
DV_C_OUT
C
10
REAR1_C_IN
C
11
fsc
12
FRONT_C_IN
C
13
FRONT_Y_IN Y
14
FRONT_V_IN
15
TO
ON SCREEN
V_TO_OSD
DV_V_OUT
Y
C
NOT
+
USED
WF12
42 40 39 38 36
41
WF13
CR
CLK DATA
ADJ
IIC LOGIC
Pre LPF2
CONV
43
C PB DIGI/PB
Y A9
CL2
REC
DIGI
WF14 Pre LPF1 ATT9 A8
REC
PB * CONV
DIGI/PB
Q501
EXT PB Y
45
DIGI
BUF Pre LPF1
A7
WF15
Q503
47
C
BUF Pre LPF2
A6
48
EXT PB C
PB REC
EXT PB C
49
VPULSE
50
51
CL1 ATT7
52
53
GCL
V5
COMP IN
54 REC
AGC
V3/V4
Y/C IN
PB
55 C1 C3
C2
AGC DET
S. SEP
56
S1/S2 DET
Y1 Y3
Y2
ATT1 ATT2
IC501
1 2 5 6 7
3
( Y/C SWITCH DV )
Y
C
Y
C
IC702
12
14 C
13
2
Y
15
Y
Y 1
2-69
C
Y
Y
C
NOT
NOT
USED
USED
34 33 32 31 30 29
EE/PB SP/EP
VHS
CL3
S-VHS
28
REC NOT
A12
PB
USED
PB
CONV
A13
REC
27
N/S-LPF
A10 CL4
EQ
PB REC A11
25
A14 CL5
CONV
CONV 24
NOT
Y
VCA
USED
REC
PB * CONV
23
22
21
N.C.
ATT8 CL6
REC PB
TRAP WF11
20
CHARADATA
19
V FBC V MUTE A1
BB
PB * D15
C WF10
18
C.K. D7&D8 NOT
BIAS
BB BB
USED
Y
V4
17
C
BB
C MUTE
A2
V3
D16 WF9
16
Y
Y FBC
15
Y
Y MUTE
A3
WF8
ATT3 ATT4 ATT5
10 11 12
8 9 14
NOT
USED
WF6 WF7
2-70
0 3 MAIN (VIDEO SW DV)
CN501
C
1
D_C_IN
TO
Y
3 D_Y/V_IN
DV ( VIDEO OUT )
Y
7 D_Y_OUT
CN3501
C
5 D_C_OUT