JVC SR-DVM70AG Schematic Diagrams page 10

DIGITAL(1394 PHY) SCHEMATIC DIAGRAM
5
4
D3.3V
PHY_RESET[L]
PHY_LREQ
PHY_CLK
PHY_CNA
TO
MEDIA PROCESSOR
PHY_CTL[0]
SHEET 4
PHY_CTL[1]
PHY_DATA[0-7]
PHY_DATA[0-7]
PHY_LPS
PHY_LINK_ON
3
GND
2
1
A
X1801
R1801 0Ω
R1802 0Ω
PHY_DATA[0]
PHY_DATA[1]
PHY_DATA[2]
PHY_DATA[3]
PHY_DATA[4]
PHY_DATA[5]
PHY_DATA[6]
PHY_DATA[7]
R1805
RA1801 RA1802
10k 10k
B C
B1802 B1801
C1806 L1802 L1801 C1804 C1803
10 0.1 10
10 µ
C1813
C1805
0.1
R1820
10k
C1810
K1801
IC1801
0Ω
D E
2-15 2-16
D3.3V
C1814
T1804 T1804 T1804 T1804
TPA1+
TPA1-
TPB1+
TPB1-
T1803 T1803 T1803 T1803
R1819 750
T1802 T1802 T1802 T1802
R1818 5.6k
TPA+
TPA0+
TPA0- TPA-
TPB0+
TPB0-
TPB+
TPB-
T1801 T1801 T1801 T1801
TPBIAS0
F
CN1802
TO JUNCTION(VIDEO)
CN7121
SHEET 23
CN1801
NOT
USED
GND
p30128001a_rev0
SHEET 6
G