Siemens SIMATIC S7-1500 Manual page 67

Configuring/address space
4.3 Manual operation (without technology object)
Explanations
Control bit/value
EN_CAPTURE
EN_SYNC_DN
EN_SYNC_UP
LD_SLOT_m
RES_EVENT
Reserved
RES_ERROR
SET_DIR
SET_DQ0
SET_DQ1
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Explanations
Use this bit to enable the Capture function. Resetting this bit resets a set EVENT_CAP in the
feedback interface.
Use this bit to enable the synchronization of the counter when counting in downward direction
with an incremental encoder or pulse encoder. Resetting this bit resets a set EVENT_SYNC in
the feedback interface.
Use this bit to enable the synchronization of the counter when counting in upward direction with
an incremental encoder or pulse encoder. Resetting this bit resets a set EVENT_SYNC in the
feedback interface.
Use this load request to specify the meaning of the value in SLOT_m:
0000 means: No action, idle
•
0001 means: Load counter value (for incremental or pulse encoder)
•
0010 not permitted
•
0011 means: Load start value (for incremental or pulse encoder)
•
0100 means: Load comparison value 0
•
0101 means: Load comparison value 1
•
0110 means: Load counting low limit (for incremental or pulse encoder)
•
0111 means: Load counting high limit (for incremental or pulse encoder)
•
1000 to 1111 not permitted
•
The technology module executes the respective action as soon as LD_SLOT_m changes.
If values are loaded simultaneously using LD_SLOT_0 and LD_SLOT_1, the value from
SLOT_0 is internally applied first and then the value from SLOT_1 . This can produce unex-
pected intermediate states.
Use this bit to trigger the reset of the saved events in the EVENT_ZERO, EVENT_OFLW,
EVENT_UFLW, EVENT_CMP0, EVENT_CMP1 feedback bits.
Reserve bits must be set to 0.
Use this bit to trigger the reset of the saved error states LD_ERROR and ENC_ERROR .
Use this bit to specify the count direction for signal type "Pulse (A)".
0 means: Up
•
1 means: Down
•
Use this bit to set digital output DQ0 when TM_CTRL_DQ0 is set to 0.
In the case of the function "After set command from CPU until comparison value", SET_DQ0 is
effective regardless of TM_CTRL_DQ0 as long as the counter value is not equal to the compar-
ison value.
Use this bit to set digital output DQ1 when TM_CTRL_DQ1 is set to 0.
In the case of the function "After set command from CPU until comparison value", SET_DQ1 is
effective regardless of TM_CTRL_DQ1 as long as the counter value is not equal to the compar-
ison value.
Technology module TM PosInput 2 (6ES7551-1AB00-0AB0)
Manual, 06/2018, A5E03982218-AB