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12
Operational Modes
•
0: Value at reset or value written by the coprocessor when previous instruction is read and its
execution is ongoing. DSP may test the status word in the output control memory to check if the
instruction is being executed.
•
1: Start - CPU orders the coprocessor to start a processing block. The first action of the coprocessor is
then to generate the first XEVT to trigger DMA transfer of the input control words.
•
2: Pause - CPU orders the coprocessor to pause a processing block at the beginning of traceback.
•
3: Unpause (single_traceback) - CPU orders the coprocessor to restart at the beginning of traceback
and halt at next traceback.
•
4: Unpause (finish_traceback) - CPU orders the coprocessor to restart at the beginning of traceback
and complete decode.
•
Stop - CPU orders the coprocessor to reset. The coprocessor resets all VCP2 registers.
12.1 Debugging Features
Visibility into the internal operation of the VCP2 (i.e., the state metric accumulation, traceback memory) is
available to the CPU via a pause command. However, since the pause command is not synchronized with
the internal VCP2 state machine but is rather sent from the CPU at a random moment in time, this feature
is of limited use.
The pause command on the VCP2 is augmented to provide visibility into VCP2 operation on a sliding
window basis. Instead of using the normal start command which tells the VCP2 to perform a complete
decode of one frame (including input/output transfers via EDMA3), halt at beginning of traceback and
resume until next traceback commands are used, and the internal VCP2 memories can be inspected at
various points in the decoding process. The procedure for using this command is as follows:
•
VCP2 configuration and branch metrics are prepared
•
A halt at beginning of traceback command is sent
•
The VCP2 generates necessary interrupts to the EDMA3 to transfer input configuration and to start
transferring branch metrics. The VCP2 performs state metric accumulation as branch metrics become
available. When it reaches the end of the first sliding window (i.e., the reliability portion and the
convergence portion), the VCP2 halts.
•
The CPU polls the VCP2 status register until the VCP2 state changes from running to paused. At that
point, the state metrics memory can be inspected, as well as the traceback memory. To perform an
inspection, halt the CPU via a software breakpoint set at an appropriate point in the code, for instance.
Then, the memory can be inspected visually via the debugger GUI, or, alternatively, the CPU can copy
the relevant internal VCP2 memories to another location for later analysis.
– The CPU sends the resume until next traceback command to the VCP2.
– The VCP2 performs the traceback, generates a portion of hard or soft decisions, and continues with
state metric accumulation until the end of the next sliding window (i.e., another number of R stages,
where R is the reliability length).
– The process continues until the decoding is complete. Alternatively, the decoding process can be
run to completion after any sliding window by sending the resume to completion command instead
of the resume until next traceback command.
SPRUE09E – May 2006 – Revised December 2009
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Copyright © 2006–2009, Texas Instruments Incorporated
TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2
Operational Modes
45
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