JVC RX-DP10VBK Service Manual page 30

RX-DP10VBK/RX-DP10VSL
RX-DP10RSL
39VF0207CWHM03 (IC667) : EEPROM
1. Pin layout
A11 1
A9 2
A8 3
A13 4
A14 5
A17 6
WE# 7
VDD 8
NC 9
A16 10
A15 11
A12 12
A7 13
A6 14
A5 15
A4 16
2. Block diagram
Memory Address
CE#
OE#
WE#
3. Pin function
Symbol Pin name
AMS- A0 Address Inputs
DQ7- DQ0 Data Input/Output
CE# Chip Enable
OE# Output Enable
WE# Write Enable
VDD Power Supply
Vss Ground
NC No Connection
1-30
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
X-Decoder
Address Buffer & Latches
Control Logic
To provide memory address. During Sector-Erase AMS-A12 address
lines will select the sector.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs
are in tri-state when OE# or CE# is high.
To active the device when CE# is low.
To gate the data output buffers.
To control the write operations.
To provide power supply voltage: 3.0-3.6V for SST39LF512/010/020/040
Unconnected Pins
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
EEPROM
Cell Array
Y-Decoder
I/O Buffers & Data Latches
DQ7~DQ0
Function
2.7-3.6V for SST39VF512/010/010/040