JVC RX-DP10VBK Service Manual page 21

2. Pin function
Pin No. Pin name I/O
21 PDN lp2
22 CKSLN lp2
23 TMD1 lp2
24 TMD0 lp2
25 VDD -
26 TOUTD O
27 TOUTA O
28 TOUT9 O
29 TOUT8 O
30 TOUT7 O
31 TOUT6 O
32 VSS -
33 VDD -
34 TOUT5 O
35 TOUT4 O
36 TOUT3 O
37 WCKO2 O
38 BCKO2 O
39 DOUT2 O
40 VSS -
41 VDD -
42 WCKO1 O
43 BCKO1 O
44 DOUT1 O
45 TOUT2 O
46 TOUT1 O
47 TOUT0 O
48 VSS -
49 VDD -
50 FP1 lp2
51 FP2 lp2
52 WSN lp2
53 WS lp2
54 RAMT lp2
55 VSS -
56 CLK l
57 VDD -
58 DFR1 lp2
59 DFR2 lp2
60 DF1 lp2
61 DF2 lp2
62 DFSEL lp2
63 SH lp2
64 VSS -
l=CMOS, l1=Schmitt, lp2=Schmitt with pull-down resistor, O=CMOS
Power down control input ; MODE=L, (L=normal, H=power down)
System clock select input ; MODE=L, (L=512fs, H=384fs)
Test input ; in normal operation this pin should be terminated to ground
Test input ; in normal operation this pin should be terminated to ground
Power supply ; All VDD pins must be connected externally
Test output ; this pin should be left open
Test output ; this pin should be left open
Test output ; this pin should be left open
Test output ; this pin should be left open
Test output ; this pin should be left open
Test output ; this pin should be left open
Ground ; All VSS pins must be connected externally
Power supply ; All VDD pins must be connected externally
Test output ; this pin should be left open
Test output ; this pin should be left open
Test output ; this pin should be left open
L/R clock output 2 ; the left or right channel for the DOUT2
Bit clock output 2 ; bit clock of serial data for the DOUT2
Serial audio data output 2
Ground ; All VSS pins must be connected externally
Power supply ; All VDD pins must be connected externally
L/R clock output 1 ; the left or right channel for the DOUT 1
Bit clock output 1; bit clock of serial data for the DOUT1
Serial audio output 1
Test output ; this pin should be left open
Test output ; this pin should be left open
Test output ; this pin should be left open
Ground ; All VSS pins must be connected externally
Power supply ; All VDD pins must be connected externally
Select FS-UP peak data compensation coefficient input 1 ; MODE=L
Select FS-UP peak data compensation coefficient input 2 ; MODE=L
Select FS-UP waveform compensation function control for 16fd to 9fd input ; MODE=L
Select FS-UP waveform compensation function control for 8fd to 2fd input ; MODE=L
RAM test control input ; in normal operation this pin should be terminated to ground
Ground ; All VSS pins must be connected externally
Master clock input ; Must run continuously normal operation, "5V tolerant"
Power supply ; All VDD pins must be connected externally
Select DF over sampling rate control 1 input for FS-UP and output 2 ; MODE=L
Select DF over sampling rate control 2 input for FS-UP and output 2 ; MODE=L
Select DF over sampling rate control 1 input for output 1 ; MODE=L
Select DF over sampling rate control 2 input for output 1 ; MODE=L
Select DF internal digital fitter ; MODE=L, (L=84tap FIR, H=169tap FIR)
Select SH mode control input ; MODE=L, (L=ON, H=OFF)
Ground ; All VSS pins must be connected externally
RX-DP10VBK/RX-DP10VSL
Function
RX-DP10RSL
(2/2)
(H=VDD, L=VSS)
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