Terminology - Intel 815EG Design Manual

Introduction
The system bus speed supported by the design is based on the capabilities of the processor,
chipset, and clock driver.
The 815 chipset for use with the universal socket 370 is not compatible with the
®
Intel Pentium
1.2

Terminology

This section describes some of the terms used in this document. Additional power delivery term
definitions are provided at the beginning of Chapter13, "Power Delivery".
Term
AGP
AGTL/AGTL+
Bus Agent
Crosstalk
GMCH
ICH
ISI
Network Length
Pad
Pin
14
®
II processor (CPUID = 066xh) 370-pin socket.
Accelerated Graphics Port
Refers to processor bus signals that are implemented using either Assisted
Gunning Transceiver Logic (AGTL+) or its lower voltage variant (AGTL), depending
on which processor is being used.
A component or group of components that, when combined, represent a single load
on the AGTL+ bus.
The reception on a victim network of a signal imposed by aggressor network(s)
through inductive and capacitive coupling between the networks.
• Backward Crosstalk–coupling that creates a signal in a victim network that travels
in the opposite direction as the aggressor's signal.
• Forward Crosstalk–coupling that creates a signal in a victim network that travels
in the same direction as the aggressor's signal.
• Even Mode Crosstalk–coupling from single or multiple aggressors when all the
aggressors switch in the same direction that the victim is switching.
• Odd Mode Crosstalk–coupling from single or multiple aggressors when all the
aggressors switch in the opposite direction that the victim is switching.
Graphics and Memory Controller Hub. A component of the Intel 815 chipset
platform for use with the Universal Socket 370
Intel 82801AA I/O Controller Hub component.
Inter-symbol interference is the effect of a previous signal (or transition) on the
interconnect delay. For example, when a signal is transmitted down a line and the
reflections due to the transition have not completely dissipated, the following data
transition launched onto the bus is affected. ISI is dependent upon frequency, time
delay of the line, and the reflection coefficient at the driver and receiver. ISI can
impact both timing and signal integrity.
The distance between agent 0 pins and the agent pins at the far end of the bus.
The electrical contact point of a semiconductor die to the package substrate. A pad
is only observable in simulation.
The contact point of a component package to the traces on a substrate such as the
motherboard. Signal quality and timings can be measured at the pin.
Description
®
Intel 815EG Chipset Platform Design Guide
R