Combination Host-Side/Device-Side Cable Detection; Figure 58. Combination Host-Side / Device-Side Ide Cable Detection - Intel 815EG Design Manual

I/O Subsystem
to the Small Form Factor Specification SFF-8049, which is obtainable from the Small Form Factor
Committee.
To determine whether the ATA/66 or ATA/100 mode can be enabled, the ICH2 requires that the
system software attempt to determine the type of cable used in the system. If the system software
detects an 80-conductor cable, it may use any Ultra DMA mode up to the highest transfer mode
supported by both the chipset and the IDE device. If a 40-conductor cable is detected, the system
software must not enable modes faster than Ultra DMA Mode 2 (Ultra ATA/33).
Intel recommends that cable detection be performed using a combination host-side/device-side
detection mechanism. Note that host-side detection cannot be implemented on an NLX form factor
system, since this configuration does not define interconnect pins for the PDIAG#/CBLID# from
the riser (containing the ATA connectors) to the motherboard. These systems must rely on the
device-side detection mechanism only.
11.2.1

Combination Host-Side/Device-Side Cable Detection

Host-side detection (described in the ATA/ATAPI-4 Standard, Section 5.2.11) requires the use of
two GPI pins (one for each IDE channel). The proper way to connect the PDIAG#/CBLID# signal
of the IDE connector to the host is shown in Figure 58. All IDE devices have a 10 kΩ pull-up
resistor to 5 V on this signal. Not all GPI and GPIO pins on the ICH2 are 5 V tolerant. If non 5 V
tolerant inputs are used, a resistor divider is required to prevent 5 V on the ICH2 or FWH pins.
The proper value of the divider resistor is 10 kΩ (as shown in Figure 58).

Figure 58. Combination Host-Side / Device-Side IDE Cable Detection

ICH2
Resistor required for
non-5V-tolerant GPI.
ICH2
Resistor required for
non-5V-tolerant GPI.
This mechanism allows BIOS, after diagnostics, to sample PDIAG#/CBLID#. If the signal is High,
then there is 40-conductor cable in the system and ATA modes 3, 4 and 5 must not be enabled.
106
To secondary
IDE connector
40-conductor
GPIO
cable
PDIAG#/
CBLID#
GPIO
10 kΩ
To secondary
IDE connector
80-conductor
GPIO
IDE cable
PDIAG#/
CBLID#
GPIO
10 kΩ
IDE drive
5 V
10 kΩ
PDIAG#
IDE drive
5 V
10 kΩ
PDIAG#
Open
®
Intel 815EG Chipset Platform Design Guide
R
IDE drive
5 V
10 kΩ
PDIAG#
IDE drive
5 V
10 kΩ
PDIAG#
IDE_combo_cable_det