Denon DN-S5000 Service Manual page 18

SM5902AF (IC651, 652)
SM5902AF Terminal Function
Pin No. Symbol I/O
1 VDD2 —
2 UC1 IP/O Microcomputer interface extended I/O 1. Not Used (OPEN)
3 UC2 IP/O Microcomputer interface extended I/O 2. Not Used (OPEN)
4 UC3 IP/O Microcomputer interface extended I/O 3. Not Used (OPEN)
5 UC4 IP/O Microcomputer interface extended I/O 4. Not Used (OPEN)
6 UC5 IP/O Microcomputer interface extended I/O 5. Not Used (OPEN)
7 DIT O
8 NTEST IP
9 CLK I
—
10 Vss
11 YSRDATA I
12 YLRCK I
13 YSCK I
14 ZSCK O
15 ZLRCK O
16 ZSRDATA O
17 YFLAG I
18 YFCLK I
19 YBLKCK I
20 NRESET I
21 ZSENSE O
22 VDD1 —
23 YDMUTE I
24 YMLD I
25 YMDATA I
26 YMCLK I
27 A10 O
28 NCAS O
29 D2 I/O
30 D3 I/O
31 D0 I/O
32 D1 I/O
33 NWE O
34 NRAS O
35 A9 O
36 A8 O
37 A7 O
38 A6 O
39 A5 O
40 A4 O
41 A0 O
42 A1 O
43 A2 O
44 A3 O
33
34
44
VDD power supply terminal.
Digital audio interface terminal.
Test terminal.
16.9344 MHz clock input.
Ground terminal.
Audio serial input data.
Audio serial input LR clock.
Audio serial input bit clock.
Audio serial output bit clock.
Audio serial output LR clock.
Audio serial output data.
RAM overflow flag for signal processing IC.
X'tal system frame clock.
Sub-code block clock signal.
System reset terminal.
Microcomputer interface status output.
VDD power supply terminal.
Forcible mute terminal.
Microcomputer interface latch clock.
Microcomputer interface serial data.
Microcomputer interface shift clock.
DRAM address 10.
DRAM CAS control.
DRAM data input/output 2.
DRAM data input/output 3.
DRAM data input/output 0.
DRAM data input/output 1.
DRAM WE control.
DRAM RAS control.
DRAM address 9.
DRAM address 8.
DRAM address 7.
DRAM address 6.
DRAM address 5.
DRAM address 4.
DRAM address 0.
DRAM address 1.
DRAM address 2.
DRAM address 3.
23
22
TOP VIEW
12
1 11
Function
18
DN-S5000 18
Setting
H L
Test
Lch Rch
Lch Rch
Over
Reset
Mute