Input Pins; Input Voltage Reference Pin; Power Management Pin; Pin Descriptions - Denon DVD-2910 Service Manual

Pin Descriptions

Input Pins

Pin Name Pin #
D23-D12 See Pin
Diagram
D11–D0 See Pin
Diagram
IDCK+ 57
IDCK- 56
DE 2
HSYNC 4
VSYNC 5

Input Voltage Reference Pin

Pin Name Pin #
VREF 3

Power Management Pin

Pin Name Pin #
PD# 10
Type Description
In Upper 12 bits of 24-bit pixel bus. Mode controlled by configuration register bit:
When BSEL = HIGH, this bus inputs the top half of the 24-bit pixel bus.
When BSEL = LOW, these bits are not used to input pixel data.
In Bottom half of 24-bit pixel bus / 12-bit pixel bus input. Mode controlled by
configuration register bit:
When BSEL = HIGH, this bus inputs the bottom half of the 24-bit pixel bus.
When BSEL = LOW, this bus inputs ½ a pixel (12-bits) at every latch edge (both
falling and/or rising) of the clock.
In Input Data Clock +. This clock is used for all input modes.
In Input Data Clock –. This clock is only used in 12-bit mode when dual edge
clocking is turned off (DSEL = LOW). It is used to provide the ODD latching edges
for multi-phased clocking. If (BSEL = HIGH) or (DSEL = HIGH) this pin is unused
and should be tied to GND.
In Data enable. This signal is high when input pixel data is valid to the transmitter
and low otherwise.
In Horizontal Sync input control signal.
In Vertical Sync input control signal.
Type Description
Analog Must be tied to 3.3V.
In
Type Description
In Power Down (active LOW). A HIGH level (3.3V) indicates normal operation and a
LOW level (GND) indicates power down mode.
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DVD-2910/955