K4S643232E (Sy: Ic717); Pin Function Description - Denon DVD-2910 Service Manual

K4S643232E (SY: IC717)

PIN CONFIGURATION
V 1
DD
DQ0 2
V 3
DDQ
DQ1 4
DQ2 5
V 6
SSQ
DQ3 7
DQ4 8
V 9
DDQ
DQ5 10
DQ6 11
V 12
SSQ
DQ7 13
N.C 14
V 15
DD
DQM0 16
WE 17
CAS 18
RAS 19
CS 20
N.C 21
BA0 22
BA1 23
A10/AP 24
A0 25
A1 26
A2 27
DQM2 28
V 29
DD
N.C 30
DQ16 31
V 32
SSQ
DQ17 33
DQ18 34
V 35
DDQ
DQ19 36
DQ20 37
V 38
SSQ
DQ21 39
DQ22 40
V 41
DDQ
DQ23 42
V 43
DD

PIN FUNCTION DESCRIPTION

Pin
CLK System clock
CS Chip select
CKE Clock enable
A ~ A Address
0 10
BA0,1 Bank select address
RAS Row address strobe
CAS Column address strobe
WE Write enable
DQM0 ~ 3 Data input/output mask
DQ ~ Data input/output
0 31
V /V Power supply/ground
DD SS
V /V Data output power/ground
DDQ SSQ
NC No Connection
BLOCK DIAGRAM
86 V
SS
DQ15
85
V
84 SSQ
DQ14
83
DQ13
82
V
81 DDQ
80 DQ12
79 DQ11
V
78
SSQ
DQ10
77
76 DQ9
V
75
DDQ
DQ8
74 CLK
73 N.C
72 V
SS
ADD
DQM1
71
N.C
70
69 N.C
CLK
68
CKE
67
66 A9
65 A8
LCKE
A7
64
A6
63
A5
62
A4
61
A3
60
59 DQM3
V
58
SS
N.C
57
56 DQ31
V
55
DDQ
DQ30
54
DQ29
53
52 V
SSQ
DQ28
51
DQ27
50
49 V
DDQ
DQ26
48
DQ25
47
46 V
SSQ
45 DQ24
V
44
SS
Name
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
Row address : RA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No connection on the device.
Bank Select
LRAS LCBR LWE LCAS
Timing Register
CLK CKE CS RAS
Input Function
~ RA , Column address : CA
0 10
after the clock and masks the output.
SHZ
57
DVD-2910/955
Data Input Register
512K x 32
512K x 32
512K x 32
512K x 32
Column Decoder
Latency & Burst Length
Programming Register
LWCBR
CAS WE DQM
~ CA
0 7
LWE
LDQM
DQi
LDQM