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Table 1.4.1(c) I/O memory map 3
Register
Address
D3
D2
0
TMRST
R
W
0F9H
HLMOD
0
R/W
0FAH
CSDC
0
R/W
0FBH
0
0
R
0FCH
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
D1
D0
Name
SR
*5
0
0
0
TMRST
R
Reset
*5
0
*5
0
0
0
HLMOD
0
*5
R
0
*5
0
*5
0
0
0
CSDC
0
*5
R
0
*5
0
*5
0
*5
0
IOC
0
*5
0
R/W
*5
0
IOC
0
CHAPTER 1: CONFIGURATION
*1
1
0
Reset
–
Clock timer reset
Heavy
Normal
Heavy load protection mode register
load
load
Static
Dynamic
LCD drive switch
Output
Input
I/O port P00–P03 Input/Output
Comment
II-7
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