Epson E0C6001 Technical Manual page 28

Fig. 4.3.2
Input interrupt circuit
configuration
(K00–K03)
Fig. 4.3.3
Input interrupt timing
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Port)
Kxx
Address
Interrupt mask
register (EIK)
Address
The interrupt mask registers (EIK00–EIK03) enable the
interrupt mask to be selected individually for K00–K03. An
interrupt occurs when the input value which are not
masked change and the interrupt factor flag (IK0) is set to 1.
Input interrupt programing related precautions
Port K input
Mask register
When the content of the mask register is rewritten, while
the port K input is in the active status. The input interrupt
factor flag is set at
When using an input interrupt, if you rewrite the content of
the mask register, when the value of the input terminal
which becomes the interrupt input is in the active status
(input terminal = high status), the factor flag for input
interrupt may be set.
For example, a factor flag is set with the timing of
in Figure 4.3.3. However, when clearing the content of the
mask register with the input terminal kept in the high
status and then setting it, the factor flag of the input inter-
rupt is again set at the timing that has been set.
One for each pin series
Noise
rejector
Mask option
(K00–K03)
Active status
Factor flag set Not set
.
Interrupt
Interrupt factor
flag (IK) request
Address
shown
I-21