Table 1.4.1(a) I/O memory map 1
Register
Address
D3
D2
K03
K02
R
0E0H
TM3
TM2
R
0E4H
EIK03
EIK02
R/W
0E8H
0
EIT2
R
0EBH
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
D1
D0
Name
SR
K01
K00
K03
–
K02
–
K01
–
K00
–
TM1
TM0
TM3
–
TM2
–
TM1
–
TM0
–
EIK01
EIK00
EIK03
0
EIK02
0
EIK01
0
EIK00
0
*5
EIT8
EIT32
0
R/W
EIT2
0
EIT8
0
EIT32
0
CHAPTER 1: CONFIGURATION
*1
1
0
*2
High
Low
*2
High
Low
Input port (K00–K03)
*2
High
Low
*2
High
Low
High
Low
Timer data (clock timer 2 Hz)
High
Low
Timer data (clock timer 4 Hz)
High
Low
Timer data (clock timer 8 Hz)
High
Low
Timer data (clock timer 16 Hz)
Enable
Mask
Interrupt mask register (K03)
Enable
Mask
Interrupt mask register (K02)
Enable
Mask
Interrupt mask register (K01)
Enable
Mask
Interrupt mask register (K00)
Enable
Mask
Interrupt mask register (clock timer 2 Hz)
Enable
Mask
Interrupt mask register (clock timer 8 Hz)
Enable
Mask
Interrupt mask register (clock timer 32 Hz)
Comment
II-5