Denon AVR-X1200W Service Manual page 139

M12L64164A-5TG2Y (DIGITAL_DSP : IC784)
ESMT
Block diagram
FUNCTIONAL BLOCK DIAGRAM
CLK
Clock
Generator
CKE
Address
CS
RAS
CAS
WE
PIN FUNCTION DESCRIPTION
PIN
CLK System Clock
Chip Select
CS
CKE Clock Enable
A0 ~ A11 Address
BA1 , BA0 Bank Select Address
Row Address Strobe
RAS
Column Address Strobe
CAS
Write Enable
WE
L(U)DQM Data Input / Output Mask
DQ0 ~ DQ15 Data Input / Output
VDD / VSS Power Supply / Ground
VDDQ / VSSQ Data Output Power / Ground
PIN CONFIGURATION (TOP VIEW)
PIN CONFIGURATION
Vdd
1
DQ0
2
VddQ
3
DQ1
4
DQ2
5
VssQ
6
DQ3
7
DQ4
8
VddQ
9
DQ5
10
DQ6
11
VssQ
12
DQ7
13
Vdd
14
LDQM
15
/WE
16
/CAS
17
/RAS
18
/CS
19
BA0
20
BA1
21
A10(AP)
22
A0
23
A1
24
A2
25
A3
26
Vdd
27
CLK : Master Clock
CKE : Clock Enable
/CS : Chip Select
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQ0-15 : Data I/O
Revision 1.0
Row
Address
Buffer
Mode
&
Register
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
NAME
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, t
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
(TOP VIEW)
Vss
54
DQ15
53
VssQ
52
DQ14
51
DQ13
50
VddQ
49
DQ12
48
DQ11
47
VssQ
46
DQ10
45
DQ9
44
VddQ
43
DQ8
42
Vss
41
NC
40
UDQM
39
CLK
38
CKE
37
NC
36
A11
35
A9
34
A8
33
A7
32
A6
31
A5
30
A4
29
Vss
28
U,LDQM : Output Disable / Write Mask
A0-11 : Address Input
BA0,1 : Bank Address
Vdd : Power Supply
VddQ : Power Supply for Output
Vss : Ground
VssQ : Ground for Output
Bank D
Bank C
Page 2/39 Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
INPUT FUNCTION
after the clock and masks the output.
SHZ
139
M12L64164A (2Y)
Dec., 2012
L(U)DQM
DQ